MOESI_hammer.py (7538:5691b9dd51f4) MOESI_hammer.py (7541:1e1f63dfd130)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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41# Note: the L2 Cache latency is not currently used
42#
43class L2Cache(RubyCache):
44 latency = 15
45
46def define_options(parser):
47 return
48
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 32 unchanged lines hidden (view full) ---

41# Note: the L2 Cache latency is not currently used
42#
43class L2Cache(RubyCache):
44 latency = 15
45
46def define_options(parser):
47 return
48
49def create_system(options, phys_mem, piobus, dma_devices):
49def create_system(options, system, piobus, dma_devices):
50
51 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
52 panic("This script requires the MOESI_hammer protocol to be built.")
53
54 cpu_sequencers = []
55
56 #
57 # The ruby network creation expects the list of nodes in the system to be

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76 l1d_cache = L1Cache(size = options.l1d_size,
77 assoc = options.l1d_assoc)
78 l2_cache = L2Cache(size = options.l2_size,
79 assoc = options.l2_assoc)
80
81 cpu_seq = RubySequencer(version = i,
82 icache = l1i_cache,
83 dcache = l1d_cache,
50
51 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
52 panic("This script requires the MOESI_hammer protocol to be built.")
53
54 cpu_sequencers = []
55
56 #
57 # The ruby network creation expects the list of nodes in the system to be

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76 l1d_cache = L1Cache(size = options.l1d_size,
77 assoc = options.l1d_assoc)
78 l2_cache = L2Cache(size = options.l2_size,
79 assoc = options.l2_assoc)
80
81 cpu_seq = RubySequencer(version = i,
82 icache = l1i_cache,
83 dcache = l1d_cache,
84 physMemPort = phys_mem.port,
85 physmem = phys_mem)
84 physMemPort = system.physmem.port,
85 physmem = system.physmem)
86
87 if piobus != None:
88 cpu_seq.pio_port = piobus.port
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 sequencer = cpu_seq,
92 L1IcacheMemory = l1i_cache,
93 L1DcacheMemory = l1d_cache,
94 L2cacheMemory = l2_cache)
86
87 if piobus != None:
88 cpu_seq.pio_port = piobus.port
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 sequencer = cpu_seq,
92 L1IcacheMemory = l1i_cache,
93 L1DcacheMemory = l1d_cache,
94 L2cacheMemory = l2_cache)
95
96 exec("system.l1_cntrl%d = l1_cntrl" % i)
95 #
96 # Add controllers and sequencers to the appropriate lists
97 #
98 cpu_sequencers.append(cpu_seq)
99 l1_cntrl_nodes.append(l1_cntrl)
100
97 #
98 # Add controllers and sequencers to the appropriate lists
99 #
100 cpu_sequencers.append(cpu_seq)
101 l1_cntrl_nodes.append(l1_cntrl)
102
101 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
103 phys_mem_size = long(system.physmem.range.second) - \
104 long(system.physmem.range.first) + 1
102 mem_module_size = phys_mem_size / options.num_dirs
103
104 for i in xrange(options.num_dirs):
105 #
106 # Create the Ruby objects associated with the directory controller
107 #
108
109 mem_cntrl = RubyMemoryControl(version = i)
110
111 dir_size = MemorySize('0B')
112 dir_size.value = mem_module_size
113
114 dir_cntrl = Directory_Controller(version = i,
115 directory = \
105 mem_module_size = phys_mem_size / options.num_dirs
106
107 for i in xrange(options.num_dirs):
108 #
109 # Create the Ruby objects associated with the directory controller
110 #
111
112 mem_cntrl = RubyMemoryControl(version = i)
113
114 dir_size = MemorySize('0B')
115 dir_size.value = mem_module_size
116
117 dir_cntrl = Directory_Controller(version = i,
118 directory = \
116 RubyDirectoryMemory(version = i,
117 size = dir_size,
118 use_map = options.use_map,
119 map_levels = options.map_levels),
119 RubyDirectoryMemory( \
120 version = i,
121 size = dir_size,
122 use_map = options.use_map,
123 map_levels = \
124 options.map_levels),
120 memBuffer = mem_cntrl)
121
125 memBuffer = mem_cntrl)
126
127 exec("system.dir_cntrl%d = dir_cntrl" % i)
122 dir_cntrl_nodes.append(dir_cntrl)
123
124 for i, dma_device in enumerate(dma_devices):
125 #
126 # Create the Ruby objects associated with the dma controller
127 #
128 dma_seq = DMASequencer(version = i,
128 dir_cntrl_nodes.append(dir_cntrl)
129
130 for i, dma_device in enumerate(dma_devices):
131 #
132 # Create the Ruby objects associated with the dma controller
133 #
134 dma_seq = DMASequencer(version = i,
129 physMemPort = phys_mem.port,
130 physmem = phys_mem)
135 physMemPort = system.physmem.port,
136 physmem = system.physmem)
131
132 dma_cntrl = DMA_Controller(version = i,
133 dma_sequencer = dma_seq)
134
137
138 dma_cntrl = DMA_Controller(version = i,
139 dma_sequencer = dma_seq)
140
141 exec("system.dma_cntrl%d = dma_cntrl" % i)
135 dma_cntrl.dma_sequencer.port = dma_device.dma
136 dma_cntrl_nodes.append(dma_cntrl)
137
138 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
139
140 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
142 dma_cntrl.dma_sequencer.port = dma_device.dma
143 dma_cntrl_nodes.append(dma_cntrl)
144
145 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
146
147 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)