MOESI_hammer.py (6893:9cdf9b65d946) MOESI_hammer.py (6897:cfeb3d9563dd)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72
73 for i in xrange(options.num_cpus):
74 #
75 # First create the Ruby objects associated with this cpu
76 #
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 60 unchanged lines hidden (view full) ---

69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72
73 for i in xrange(options.num_cpus):
74 #
75 # First create the Ruby objects associated with this cpu
76 #
77 l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i))
78 l1i_cache = L1Cache(cache_profiler = l1i_profiler)
77 l1i_cache = L1Cache()
78 l1d_cache = L1Cache()
79 l2_cache = L2Cache()
79
80
80 l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i))
81 l1d_cache = L1Cache(cache_profiler = l1d_profiler)
82
83 l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i))
84 l2_cache = L2Cache(cache_profiler = l2_profiler)
85
86 cpu_seq = RubySequencer(icache = l1i_cache,
87 dcache = l1d_cache,
88 physMemPort = phys_mem.port,
89 physmem = phys_mem)
90
91 if piobus != None:
92 cpu_seq.pio_port = piobus.port
93

--- 42 unchanged lines hidden --- 		81 cpu_seq = RubySequencer(icache = l1i_cache,
82 dcache = l1d_cache,
83 physMemPort = phys_mem.port,
84 physmem = phys_mem)
85
86 if piobus != None:
87 cpu_seq.pio_port = piobus.port
88

--- 42 unchanged lines hidden ---