MOESI_hammer.py (11065:37e19af67f62) MOESI_hammer.py (11266:452e10b868ea)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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84 is_icache = True)
85 l1d_cache = L1Cache(size = options.l1d_size,
86 assoc = options.l1d_assoc,
87 start_index_bit = block_size_bits)
88 l2_cache = L2Cache(size = options.l2_size,
89 assoc = options.l2_assoc,
90 start_index_bit = block_size_bits)
91
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 75 unchanged lines hidden (view full) ---

84 is_icache = True)
85 l1d_cache = L1Cache(size = options.l1d_size,
86 assoc = options.l1d_assoc,
87 start_index_bit = block_size_bits)
88 l2_cache = L2Cache(size = options.l2_size,
89 assoc = options.l2_assoc,
90 start_index_bit = block_size_bits)
91
92 l1_cntrl = L1Cache_Controller(version = i,
93 L1Icache = l1i_cache,
94 L1Dcache = l1d_cache,
95 L2cache = l2_cache,
96 no_mig_atomic = not \
97 options.allow_atomic_migration,
98 send_evictions = send_evicts(options),
99 transitions_per_cycle = options.ports,
100 clk_domain=system.cpu[i].clk_domain,
101 ruby_system = ruby_system)
92 # the ruby random tester reuses num_cpus to specify the
93 # number of cpu ports connected to the tester object, which
94 # is stored in system.cpu. because there is only ever one
95 # tester object, num_cpus is not necessarily equal to the
96 # size of system.cpu; therefore if len(system.cpu) == 1
97 # we use system.cpu[0] to set the clk_domain, thereby ensuring
98 # we don't index off the end of the cpu list.
99 if len(system.cpu) == 1:
100 clk_domain = system.cpu[0].clk_domain
101 else:
102 clk_domain = system.cpu[i].clk_domain
102
103
103 cpu_seq = RubySequencer(version = i,
104 icache = l1i_cache,
105 dcache = l1d_cache,
106 clk_domain=system.cpu[i].clk_domain,
107 ruby_system = ruby_system)
104 l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
105 L1Dcache=l1d_cache, L2cache=l2_cache,
106 no_mig_atomic=not \
107 options.allow_atomic_migration,
108 send_evictions=send_evicts(options),
109 transitions_per_cycle=options.ports,
110 clk_domain=clk_domain,
111 ruby_system=ruby_system)
108
112
113 cpu_seq = RubySequencer(version=i, icache=l1i_cache,
114 dcache=l1d_cache,clk_domain=clk_domain,
115 ruby_system=ruby_system)
116
109 l1_cntrl.sequencer = cpu_seq
110 if options.recycle_latency:
111 l1_cntrl.recycle_latency = options.recycle_latency
112
113 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
114
115 # Add controllers and sequencers to the appropriate lists
116 cpu_sequencers.append(cpu_seq)

--- 147 unchanged lines hidden --- 		117 l1_cntrl.sequencer = cpu_seq
118 if options.recycle_latency:
119 l1_cntrl.recycle_latency = options.recycle_latency
120
121 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
122
123 # Add controllers and sequencers to the appropriate lists
124 cpu_sequencers.append(cpu_seq)

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