MOESI_hammer.py (10524:fff17530cef6) | MOESI_hammer.py (10529:05b5a6cf3521) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology |
35from Ruby import send_evicts |
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35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 latency = 2 41 42# --- 54 unchanged lines hidden (view full) --- 97 start_index_bit = block_size_bits) 98 99 l1_cntrl = L1Cache_Controller(version = i, 100 L1Icache = l1i_cache, 101 L1Dcache = l1d_cache, 102 L2cache = l2_cache, 103 no_mig_atomic = not \ 104 options.allow_atomic_migration, | 36 37# 38# Note: the L1 Cache latency is only used by the sequencer on fast path hits 39# 40class L1Cache(RubyCache): 41 latency = 2 42 43# --- 54 unchanged lines hidden (view full) --- 98 start_index_bit = block_size_bits) 99 100 l1_cntrl = L1Cache_Controller(version = i, 101 L1Icache = l1i_cache, 102 L1Dcache = l1d_cache, 103 L2cache = l2_cache, 104 no_mig_atomic = not \ 105 options.allow_atomic_migration, |
105 send_evictions = ( 106 options.cpu_type == "detailed"), | 106 send_evictions = send_evicts(options), |
107 transitions_per_cycle = options.ports, 108 clk_domain=system.cpu[i].clk_domain, 109 ruby_system = ruby_system) 110 111 cpu_seq = RubySequencer(version = i, 112 icache = l1i_cache, 113 dcache = l1d_cache, 114 clk_domain=system.cpu[i].clk_domain, --- 132 unchanged lines hidden --- | 107 transitions_per_cycle = options.ports, 108 clk_domain=system.cpu[i].clk_domain, 109 ruby_system = ruby_system) 110 111 cpu_seq = RubySequencer(version = i, 112 icache = l1i_cache, 113 dcache = l1d_cache, 114 clk_domain=system.cpu[i].clk_domain, --- 132 unchanged lines hidden --- |