MOESI_hammer.py (10300:ed3816dae6d5) | MOESI_hammer.py (10311:ad9c042dce54) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 105 unchanged lines hidden (view full) --- 114 clk_domain=system.cpu[i].clk_domain, 115 ruby_system = ruby_system) 116 117 l1_cntrl.sequencer = cpu_seq 118 if options.recycle_latency: 119 l1_cntrl.recycle_latency = options.recycle_latency 120 121 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 105 unchanged lines hidden (view full) --- 114 clk_domain=system.cpu[i].clk_domain, 115 ruby_system = ruby_system) 116 117 l1_cntrl.sequencer = cpu_seq 118 if options.recycle_latency: 119 l1_cntrl.recycle_latency = options.recycle_latency 120 121 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) |
122 # | 122 |
123 # Add controllers and sequencers to the appropriate lists | 123 # Add controllers and sequencers to the appropriate lists |
124 # | |
125 cpu_sequencers.append(cpu_seq) 126 l1_cntrl_nodes.append(l1_cntrl) 127 | 124 cpu_sequencers.append(cpu_seq) 125 l1_cntrl_nodes.append(l1_cntrl) 126 |
127 # Connect the L1 controller and the network 128 # Connect the buffers from the controller to network 129 l1_cntrl.requestFromCache = ruby_system.network.slave 130 l1_cntrl.responseFromCache = ruby_system.network.slave 131 l1_cntrl.unblockFromCache = ruby_system.network.slave 132 133 # Connect the buffers from the network to the controller 134 l1_cntrl.forwardToCache = ruby_system.network.master 135 l1_cntrl.responseToCache = ruby_system.network.master 136 137 |
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128 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 129 assert(phys_mem_size % options.num_dirs == 0) 130 mem_module_size = phys_mem_size / options.num_dirs 131 132 # 133 # determine size and index bits for probe filter 134 # By default, the probe filter size is configured to be twice the 135 # size of the L2 cache. --- 57 unchanged lines hidden (view full) --- 193 ruby_system = ruby_system) 194 195 if options.recycle_latency: 196 dir_cntrl.recycle_latency = options.recycle_latency 197 198 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 199 dir_cntrl_nodes.append(dir_cntrl) 200 | 138 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 139 assert(phys_mem_size % options.num_dirs == 0) 140 mem_module_size = phys_mem_size / options.num_dirs 141 142 # 143 # determine size and index bits for probe filter 144 # By default, the probe filter size is configured to be twice the 145 # size of the L2 cache. --- 57 unchanged lines hidden (view full) --- 203 ruby_system = ruby_system) 204 205 if options.recycle_latency: 206 dir_cntrl.recycle_latency = options.recycle_latency 207 208 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 209 dir_cntrl_nodes.append(dir_cntrl) 210 |
211 # Connect the directory controller to the network 212 dir_cntrl.forwardFromDir = ruby_system.network.slave 213 dir_cntrl.responseFromDir = ruby_system.network.slave 214 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave 215 216 dir_cntrl.unblockToDir = ruby_system.network.master 217 dir_cntrl.responseToDir = ruby_system.network.master 218 dir_cntrl.requestToDir = ruby_system.network.master 219 dir_cntrl.dmaRequestToDir = ruby_system.network.master 220 221 |
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201 for i, dma_port in enumerate(dma_ports): 202 # 203 # Create the Ruby objects associated with the dma controller 204 # 205 dma_seq = DMASequencer(version = i, 206 ruby_system = ruby_system) 207 208 dma_cntrl = DMA_Controller(version = i, 209 dma_sequencer = dma_seq, 210 transitions_per_cycle = options.ports, 211 ruby_system = ruby_system) 212 213 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 214 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 215 dma_cntrl_nodes.append(dma_cntrl) 216 217 if options.recycle_latency: 218 dma_cntrl.recycle_latency = options.recycle_latency 219 | 222 for i, dma_port in enumerate(dma_ports): 223 # 224 # Create the Ruby objects associated with the dma controller 225 # 226 dma_seq = DMASequencer(version = i, 227 ruby_system = ruby_system) 228 229 dma_cntrl = DMA_Controller(version = i, 230 dma_sequencer = dma_seq, 231 transitions_per_cycle = options.ports, 232 ruby_system = ruby_system) 233 234 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 235 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 236 dma_cntrl_nodes.append(dma_cntrl) 237 238 if options.recycle_latency: 239 dma_cntrl.recycle_latency = options.recycle_latency 240 |
241 # Connect the dma controller to the network 242 dma_cntrl.responseFromDir = ruby_system.network.slave 243 dma_cntrl.requestToDir = ruby_system.network.master 244 245 |
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220 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 221 topology = create_topology(all_cntrls, options) | 246 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 247 topology = create_topology(all_cntrls, options) |
222 | |
223 return (cpu_sequencers, dir_cntrl_nodes, topology) | 248 return (cpu_sequencers, dir_cntrl_nodes, topology) |