1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 # 127 # Add controllers and sequencers to the appropriate lists 128 # 129 cpu_sequencers.append(cpu_seq) 130 l1_cntrl_nodes.append(l1_cntrl) 131 132 cntrl_count += 1 133 |
134 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) |
135 assert(phys_mem_size % options.num_dirs == 0) 136 mem_module_size = phys_mem_size / options.num_dirs 137 138 # 139 # determine size and index bits for probe filter 140 # By default, the probe filter size is configured to be twice the 141 # size of the L2 cache. 142 # --- 92 unchanged lines hidden --- |