1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 74 unchanged lines hidden (view full) --- 83 cntrl_count = 0 84 85 for i in xrange(options.num_cpus): 86 # 87 # First create the Ruby objects associated with this cpu 88 # 89 l1i_cache = L1Cache(size = options.l1i_size, 90 assoc = options.l1i_assoc, |
91 start_index_bit = block_size_bits, 92 is_icache = True) |
93 l1d_cache = L1Cache(size = options.l1d_size, 94 assoc = options.l1d_assoc, 95 start_index_bit = block_size_bits) 96 l2_cache = L2Cache(size = options.l2_size, 97 assoc = options.l2_assoc, 98 start_index_bit = block_size_bits) 99 100 l1_cntrl = L1Cache_Controller(version = i, --- 126 unchanged lines hidden --- |