1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 186 unchanged lines hidden (view full) --- 195 cntrl_count += 1 196 197 for i, dma_device in enumerate(dma_devices): 198 # 199 # Create the Ruby objects associated with the dma controller 200 # 201 dma_seq = DMASequencer(version = i, 202 physMemPort = system.physmem.port, |
203 physmem = system.physmem, 204 ruby_system = ruby_system) |
205 206 dma_cntrl = DMA_Controller(version = i, 207 cntrl_id = cntrl_count, |
208 dma_sequencer = dma_seq, 209 ruby_system = ruby_system) |
210 211 exec("system.dma_cntrl%d = dma_cntrl" % i) 212 if dma_device.type == 'MemTest': 213 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 214 else: 215 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 216 dma_cntrl_nodes.append(dma_cntrl) 217 218 if options.recycle_latency: 219 dma_cntrl.recycle_latency = options.recycle_latency 220 221 cntrl_count += 1 222 223 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 224 225 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |