1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32from m5.defines import buildEnv 33from m5.util import addToPath 34 35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): |
40 latency = 3 |
41 42# 43# Note: the L2 Cache latency is not currently used 44# 45class L2Cache(RubyCache): |
46 latency = 15 |
47 48def create_system(options, phys_mem, piobus, dma_devices): 49 50 if buildEnv['PROTOCOL'] != 'MOESI_hammer': 51 panic("This script requires the MOESI_hammer protocol to be built.") 52 53 cpu_sequencers = [] 54 --- 10 unchanged lines hidden (view full) --- 65 # Must create the individual controllers before the network to ensure the 66 # controller constructors are called before the network constructor 67 # 68 69 for i in xrange(options.num_cpus): 70 # 71 # First create the Ruby objects associated with this cpu 72 # |
73 l1i_cache = L1Cache(size = options.l1i_size, 74 assoc = options.l1i_assoc) 75 l1d_cache = L1Cache(size = options.l1d_size, 76 assoc = options.l1d_assoc) 77 l2_cache = L2Cache(size = options.l2_size, 78 assoc = options.l2_assoc) |
79 80 cpu_seq = RubySequencer(icache = l1i_cache, 81 dcache = l1d_cache, 82 physMemPort = phys_mem.port, 83 physmem = phys_mem) 84 85 if piobus != None: 86 cpu_seq.pio_port = piobus.port --- 43 unchanged lines hidden --- |