1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 104 unchanged lines hidden (view full) --- 113 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 114 115 # Add controllers and sequencers to the appropriate lists 116 cpu_sequencers.append(cpu_seq) 117 l1_cntrl_nodes.append(l1_cntrl) 118 119 # Connect the L1 controller and the network 120 # Connect the buffers from the controller to network |
121 l1_cntrl.requestFromCache = MessageBuffer() 122 l1_cntrl.requestFromCache.master = ruby_system.network.slave 123 l1_cntrl.responseFromCache = MessageBuffer() 124 l1_cntrl.responseFromCache.master = ruby_system.network.slave 125 l1_cntrl.unblockFromCache = MessageBuffer() 126 l1_cntrl.unblockFromCache.master = ruby_system.network.slave |
127 |
128 l1_cntrl.triggerQueue = MessageBuffer() 129 |
130 # Connect the buffers from the network to the controller |
131 l1_cntrl.mandatoryQueue = MessageBuffer() 132 l1_cntrl.forwardToCache = MessageBuffer() 133 l1_cntrl.forwardToCache.slave = ruby_system.network.master 134 l1_cntrl.responseToCache = MessageBuffer() 135 l1_cntrl.responseToCache.slave = ruby_system.network.master |
136 137 138 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 139 assert(phys_mem_size % options.num_dirs == 0) 140 mem_module_size = phys_mem_size / options.num_dirs 141 142 # 143 # determine size and index bits for probe filter --- 43 unchanged lines hidden (view full) --- 187 188 if options.recycle_latency: 189 dir_cntrl.recycle_latency = options.recycle_latency 190 191 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 192 dir_cntrl_nodes.append(dir_cntrl) 193 194 # Connect the directory controller to the network |
195 dir_cntrl.forwardFromDir = MessageBuffer() 196 dir_cntrl.forwardFromDir.master = ruby_system.network.slave 197 dir_cntrl.responseFromDir = MessageBuffer() 198 dir_cntrl.responseFromDir.master = ruby_system.network.slave 199 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) 200 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave |
201 |
202 dir_cntrl.triggerQueue = MessageBuffer(ordered = True) |
203 |
204 dir_cntrl.unblockToDir = MessageBuffer() 205 dir_cntrl.unblockToDir.slave = ruby_system.network.master 206 dir_cntrl.responseToDir = MessageBuffer() 207 dir_cntrl.responseToDir.slave = ruby_system.network.master 208 dir_cntrl.requestToDir = MessageBuffer() 209 dir_cntrl.requestToDir.slave = ruby_system.network.master 210 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) 211 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master 212 dir_cntrl.responseFromMemory = MessageBuffer() |
213 |
214 |
215 for i, dma_port in enumerate(dma_ports): 216 # 217 # Create the Ruby objects associated with the dma controller 218 # 219 dma_seq = DMASequencer(version = i, 220 ruby_system = ruby_system, 221 slave = dma_port) 222 --- 4 unchanged lines hidden (view full) --- 227 228 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 229 dma_cntrl_nodes.append(dma_cntrl) 230 231 if options.recycle_latency: 232 dma_cntrl.recycle_latency = options.recycle_latency 233 234 # Connect the dma controller to the network |
235 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 236 dma_cntrl.responseFromDir.slave = ruby_system.network.master 237 dma_cntrl.requestToDir = MessageBuffer() 238 dma_cntrl.requestToDir.master = ruby_system.network.slave 239 dma_cntrl.mandatoryQueue = MessageBuffer() |
240 241 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 242 243 # Create the io controller and the sequencer 244 if full_system: 245 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 246 ruby_system._io_port = io_seq 247 io_controller = DMA_Controller(version = len(dma_ports), 248 dma_sequencer = io_seq, 249 ruby_system = ruby_system) 250 ruby_system.io_controller = io_controller 251 252 # Connect the dma controller to the network |
253 io_controller.responseFromDir = MessageBuffer(ordered = True) 254 io_controller.responseFromDir.slave = ruby_system.network.master 255 io_controller.requestToDir = MessageBuffer() 256 io_controller.requestToDir.master = ruby_system.network.slave 257 io_controller.mandatoryQueue = MessageBuffer() |
258 259 all_cntrls = all_cntrls + [io_controller] 260 261 topology = create_topology(all_cntrls, options) 262 return (cpu_sequencers, dir_cntrl_nodes, topology) |