1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 101 unchanged lines hidden (view full) --- 110 cpu_seq = RubySequencer(version = i, 111 icache = l1i_cache, 112 dcache = l1d_cache, 113 ruby_system = ruby_system) 114 115 l1_cntrl.sequencer = cpu_seq 116 117 if piobus != None: |
118 cpu_seq.pio_master_port = piobus.slave 119 cpu_seq.mem_master_port = piobus.slave 120 cpu_seq.pio_slave_port = piobus.master |
121 122 if options.recycle_latency: 123 l1_cntrl.recycle_latency = options.recycle_latency 124 125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 126 # 127 # Add controllers and sequencers to the appropriate lists 128 # --- 99 unchanged lines hidden --- |