98a99,106
> l1_cntrl = L1Cache_Controller(version = i,
> cntrl_id = cntrl_count,
> L1IcacheMemory = l1i_cache,
> L1DcacheMemory = l1d_cache,
> L2cacheMemory = l2_cache,
> no_mig_atomic = not \
> options.allow_atomic_migration)
>
104a113,114
> l1_cntrl.sequencer = cpu_seq
>
108,116d117
< l1_cntrl = L1Cache_Controller(version = i,
< cntrl_id = cntrl_count,
< sequencer = cpu_seq,
< L1IcacheMemory = l1i_cache,
< L1DcacheMemory = l1d_cache,
< L2cacheMemory = l2_cache,
< no_mig_atomic = not \
< options.allow_atomic_migration)
<