52c52
< def create_system(options, physmem):
---
> def create_system(options, phys_mem, piobus, dma_devices):
57c57,58
< sequencers = []
---
> cpu_sequencers = []
>
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< for i in range(options.num_cpus):
---
>
> for i in xrange(options.num_cpus):
74,75d75
< # Eventually this code should go in a python file specific to the
< # MOESI_hammer protocol
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< funcmem_port = physmem.port)
---
> physMemPort = phys_mem.port,
> physmem = phys_mem)
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> if piobus != None:
> cpu_seq.pio_port = piobus.port
>
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> #
> # Add controllers and sequencers to the appropriate lists
> #
> cpu_sequencers.append(cpu_seq)
> l1_cntrl_nodes.append(l1_cntrl)
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> for i in xrange(options.num_dirs):
> #
> # Create the Ruby objects associated with the directory controller
> #
>
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< directory = RubyDirectoryMemory(),
---
> directory = \
> RubyDirectoryMemory(version = i),
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< dma_cntrl = DMA_Controller(version = i,
< dma_sequencer = DMASequencer())
---
> dir_cntrl_nodes.append(dir_cntrl)
104a119
> for i, dma_device in enumerate(dma_devices):
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< # Add controllers and sequencers to the appropriate lists
< # As noted above: Independent list are track to maintain the order of
< # nodes/controllers assumed by the ruby network
---
> # Create the Ruby objects associated with the dma controller
110,112c123,130
< sequencers.append(cpu_seq)
< l1_cntrl_nodes.append(l1_cntrl)
< dir_cntrl_nodes.append(dir_cntrl)
---
> dma_seq = DMASequencer(version = i,
> physMemPort = phys_mem.port,
> physmem = phys_mem)
>
> dma_cntrl = DMA_Controller(version = i,
> dma_sequencer = dma_seq)
>
> dma_cntrl.dma_sequencer.port = dma_device.dma
117c135
< return (sequencers, dir_cntrl_nodes, all_cntrls)
---
> return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)