1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39 latency = 2
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 10
46
47#
48# Probe filter is a cache, latency is not used
49#
50class ProbeFilter(RubyCache):
51 latency = 1
52
53def define_options(parser):
54 parser.add_option("--allow-atomic-migration", action="store_true",
55 help="allow migratory sharing for atomic only accessed blocks")
56 parser.add_option("--pf-on", action="store_true",
57 help="Hammer: enable Probe Filter")
58 parser.add_option("--dir-on", action="store_true",
59 help="Hammer: enable Full-bit Directory")
60
61def create_system(options, system, piobus, dma_devices):
62
63 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
64 panic("This script requires the MOESI_hammer protocol to be built.")
65
66 cpu_sequencers = []
67
68 #
69 # The ruby network creation expects the list of nodes in the system to be
70 # consistent with the NetDest list. Therefore the l1 controller nodes must be
71 # listed before the directory nodes and directory nodes before dma nodes, etc.
72 #
73 l1_cntrl_nodes = []
74 dir_cntrl_nodes = []
75 dma_cntrl_nodes = []
76
77 #
78 # Must create the individual controllers before the network to ensure the
79 # controller constructors are called before the network constructor
80 #
81 block_size_bits = int(math.log(options.cacheline_size, 2))
82
83 cntrl_count = 0
84
85 for i in xrange(options.num_cpus):
86 #
87 # First create the Ruby objects associated with this cpu
88 #
89 l1i_cache = L1Cache(size = options.l1i_size,
90 assoc = options.l1i_assoc,
91 start_index_bit = block_size_bits)
92 l1d_cache = L1Cache(size = options.l1d_size,
93 assoc = options.l1d_assoc,
94 start_index_bit = block_size_bits)
95 l2_cache = L2Cache(size = options.l2_size,
96 assoc = options.l2_assoc,
97 start_index_bit = block_size_bits)
98
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39 latency = 2
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 10
46
47#
48# Probe filter is a cache, latency is not used
49#
50class ProbeFilter(RubyCache):
51 latency = 1
52
53def define_options(parser):
54 parser.add_option("--allow-atomic-migration", action="store_true",
55 help="allow migratory sharing for atomic only accessed blocks")
56 parser.add_option("--pf-on", action="store_true",
57 help="Hammer: enable Probe Filter")
58 parser.add_option("--dir-on", action="store_true",
59 help="Hammer: enable Full-bit Directory")
60
61def create_system(options, system, piobus, dma_devices):
62
63 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
64 panic("This script requires the MOESI_hammer protocol to be built.")
65
66 cpu_sequencers = []
67
68 #
69 # The ruby network creation expects the list of nodes in the system to be
70 # consistent with the NetDest list. Therefore the l1 controller nodes must be
71 # listed before the directory nodes and directory nodes before dma nodes, etc.
72 #
73 l1_cntrl_nodes = []
74 dir_cntrl_nodes = []
75 dma_cntrl_nodes = []
76
77 #
78 # Must create the individual controllers before the network to ensure the
79 # controller constructors are called before the network constructor
80 #
81 block_size_bits = int(math.log(options.cacheline_size, 2))
82
83 cntrl_count = 0
84
85 for i in xrange(options.num_cpus):
86 #
87 # First create the Ruby objects associated with this cpu
88 #
89 l1i_cache = L1Cache(size = options.l1i_size,
90 assoc = options.l1i_assoc,
91 start_index_bit = block_size_bits)
92 l1d_cache = L1Cache(size = options.l1d_size,
93 assoc = options.l1d_assoc,
94 start_index_bit = block_size_bits)
95 l2_cache = L2Cache(size = options.l2_size,
96 assoc = options.l2_assoc,
97 start_index_bit = block_size_bits)
98
|
| 99 l1_cntrl = L1Cache_Controller(version = i,
100 cntrl_id = cntrl_count,
101 L1IcacheMemory = l1i_cache,
102 L1DcacheMemory = l1d_cache,
103 L2cacheMemory = l2_cache,
104 no_mig_atomic = not \
105 options.allow_atomic_migration)
106
|
99 cpu_seq = RubySequencer(version = i,
100 icache = l1i_cache,
101 dcache = l1d_cache,
102 physMemPort = system.physmem.port,
103 physmem = system.physmem)
104
| 107 cpu_seq = RubySequencer(version = i,
108 icache = l1i_cache,
109 dcache = l1d_cache,
110 physMemPort = system.physmem.port,
111 physmem = system.physmem)
112
|
| 113 l1_cntrl.sequencer = cpu_seq
114
|
105 if piobus != None:
106 cpu_seq.pio_port = piobus.port
107
| 115 if piobus != None:
116 cpu_seq.pio_port = piobus.port
117
|
108 l1_cntrl = L1Cache_Controller(version = i,
109 cntrl_id = cntrl_count,
110 sequencer = cpu_seq,
111 L1IcacheMemory = l1i_cache,
112 L1DcacheMemory = l1d_cache,
113 L2cacheMemory = l2_cache,
114 no_mig_atomic = not \
115 options.allow_atomic_migration)
116
| |
117 if options.recycle_latency:
118 l1_cntrl.recycle_latency = options.recycle_latency
119
120 exec("system.l1_cntrl%d = l1_cntrl" % i)
121 #
122 # Add controllers and sequencers to the appropriate lists
123 #
124 cpu_sequencers.append(cpu_seq)
125 l1_cntrl_nodes.append(l1_cntrl)
126
127 cntrl_count += 1
128
129 phys_mem_size = long(system.physmem.range.second) - \
130 long(system.physmem.range.first) + 1
131 mem_module_size = phys_mem_size / options.num_dirs
132
133 #
134 # determine size and index bits for probe filter
135 # By default, the probe filter size is configured to be twice the
136 # size of the L2 cache.
137 #
138 pf_size = MemorySize(options.l2_size)
139 pf_size.value = pf_size.value * 2
140 dir_bits = int(math.log(options.num_dirs, 2))
141 pf_bits = int(math.log(pf_size.value, 2))
142 if options.numa_high_bit:
143 if options.numa_high_bit > 0:
144 # if numa high bit explicitly set, make sure it does not overlap
145 # with the probe filter index
146 assert(options.numa_high_bit - dir_bits > pf_bits)
147
148 # set the probe filter start bit to just above the block offset
149 pf_start_bit = 6
150 else:
151 if dir_bits > 0:
152 pf_start_bit = dir_bits + 5
153 else:
154 pf_start_bit = 6
155
156 for i in xrange(options.num_dirs):
157 #
158 # Create the Ruby objects associated with the directory controller
159 #
160
161 mem_cntrl = RubyMemoryControl(version = i)
162
163 dir_size = MemorySize('0B')
164 dir_size.value = mem_module_size
165
166 pf = ProbeFilter(size = pf_size, assoc = 4,
167 start_index_bit = pf_start_bit)
168
169 dir_cntrl = Directory_Controller(version = i,
170 cntrl_id = cntrl_count,
171 directory = \
172 RubyDirectoryMemory( \
173 version = i,
174 size = dir_size,
175 use_map = options.use_map,
176 map_levels = \
177 options.map_levels,
178 numa_high_bit = \
179 options.numa_high_bit),
180 probeFilter = pf,
181 memBuffer = mem_cntrl,
182 probe_filter_enabled = options.pf_on,
183 full_bit_dir_enabled = options.dir_on)
184
185 if options.recycle_latency:
186 dir_cntrl.recycle_latency = options.recycle_latency
187
188 exec("system.dir_cntrl%d = dir_cntrl" % i)
189 dir_cntrl_nodes.append(dir_cntrl)
190
191 cntrl_count += 1
192
193 for i, dma_device in enumerate(dma_devices):
194 #
195 # Create the Ruby objects associated with the dma controller
196 #
197 dma_seq = DMASequencer(version = i,
198 physMemPort = system.physmem.port,
199 physmem = system.physmem)
200
201 dma_cntrl = DMA_Controller(version = i,
202 cntrl_id = cntrl_count,
203 dma_sequencer = dma_seq)
204
205 exec("system.dma_cntrl%d = dma_cntrl" % i)
206 if dma_device.type == 'MemTest':
207 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
208 else:
209 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
210 dma_cntrl_nodes.append(dma_cntrl)
211
212 if options.recycle_latency:
213 dma_cntrl.recycle_latency = options.recycle_latency
214
215 cntrl_count += 1
216
217 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
218
219 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
| 118 if options.recycle_latency:
119 l1_cntrl.recycle_latency = options.recycle_latency
120
121 exec("system.l1_cntrl%d = l1_cntrl" % i)
122 #
123 # Add controllers and sequencers to the appropriate lists
124 #
125 cpu_sequencers.append(cpu_seq)
126 l1_cntrl_nodes.append(l1_cntrl)
127
128 cntrl_count += 1
129
130 phys_mem_size = long(system.physmem.range.second) - \
131 long(system.physmem.range.first) + 1
132 mem_module_size = phys_mem_size / options.num_dirs
133
134 #
135 # determine size and index bits for probe filter
136 # By default, the probe filter size is configured to be twice the
137 # size of the L2 cache.
138 #
139 pf_size = MemorySize(options.l2_size)
140 pf_size.value = pf_size.value * 2
141 dir_bits = int(math.log(options.num_dirs, 2))
142 pf_bits = int(math.log(pf_size.value, 2))
143 if options.numa_high_bit:
144 if options.numa_high_bit > 0:
145 # if numa high bit explicitly set, make sure it does not overlap
146 # with the probe filter index
147 assert(options.numa_high_bit - dir_bits > pf_bits)
148
149 # set the probe filter start bit to just above the block offset
150 pf_start_bit = 6
151 else:
152 if dir_bits > 0:
153 pf_start_bit = dir_bits + 5
154 else:
155 pf_start_bit = 6
156
157 for i in xrange(options.num_dirs):
158 #
159 # Create the Ruby objects associated with the directory controller
160 #
161
162 mem_cntrl = RubyMemoryControl(version = i)
163
164 dir_size = MemorySize('0B')
165 dir_size.value = mem_module_size
166
167 pf = ProbeFilter(size = pf_size, assoc = 4,
168 start_index_bit = pf_start_bit)
169
170 dir_cntrl = Directory_Controller(version = i,
171 cntrl_id = cntrl_count,
172 directory = \
173 RubyDirectoryMemory( \
174 version = i,
175 size = dir_size,
176 use_map = options.use_map,
177 map_levels = \
178 options.map_levels,
179 numa_high_bit = \
180 options.numa_high_bit),
181 probeFilter = pf,
182 memBuffer = mem_cntrl,
183 probe_filter_enabled = options.pf_on,
184 full_bit_dir_enabled = options.dir_on)
185
186 if options.recycle_latency:
187 dir_cntrl.recycle_latency = options.recycle_latency
188
189 exec("system.dir_cntrl%d = dir_cntrl" % i)
190 dir_cntrl_nodes.append(dir_cntrl)
191
192 cntrl_count += 1
193
194 for i, dma_device in enumerate(dma_devices):
195 #
196 # Create the Ruby objects associated with the dma controller
197 #
198 dma_seq = DMASequencer(version = i,
199 physMemPort = system.physmem.port,
200 physmem = system.physmem)
201
202 dma_cntrl = DMA_Controller(version = i,
203 cntrl_id = cntrl_count,
204 dma_sequencer = dma_seq)
205
206 exec("system.dma_cntrl%d = dma_cntrl" % i)
207 if dma_device.type == 'MemTest':
208 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
209 else:
210 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
211 dma_cntrl_nodes.append(dma_cntrl)
212
213 if options.recycle_latency:
214 dma_cntrl.recycle_latency = options.recycle_latency
215
216 cntrl_count += 1
217
218 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
219
220 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|