1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33
34#
35# Note: the L1 Cache latency is only used by the sequencer on fast path hits
36#
37class L1Cache(RubyCache):
38 latency = 3
39
40#
41# Note: the L2 Cache latency is not currently used
42#
43class L2Cache(RubyCache):
44 latency = 15
45
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33
34#
35# Note: the L1 Cache latency is only used by the sequencer on fast path hits
36#
37class L1Cache(RubyCache):
38 latency = 3
39
40#
41# Note: the L2 Cache latency is not currently used
42#
43class L2Cache(RubyCache):
44 latency = 15
45
|
46def create_system(options, phys_mem, piobus, dma_devices):
47
48 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
49 panic("This script requires the MOESI_hammer protocol to be built.")
50
51 cpu_sequencers = []
52
53 #
54 # The ruby network creation expects the list of nodes in the system to be
55 # consistent with the NetDest list. Therefore the l1 controller nodes must be
56 # listed before the directory nodes and directory nodes before dma nodes, etc.
57 #
58 l1_cntrl_nodes = []
59 dir_cntrl_nodes = []
60 dma_cntrl_nodes = []
61
62 #
63 # Must create the individual controllers before the network to ensure the
64 # controller constructors are called before the network constructor
65 #
66
67 for i in xrange(options.num_cpus):
68 #
69 # First create the Ruby objects associated with this cpu
70 #
71 l1i_cache = L1Cache(size = options.l1i_size,
72 assoc = options.l1i_assoc)
73 l1d_cache = L1Cache(size = options.l1d_size,
74 assoc = options.l1d_assoc)
75 l2_cache = L2Cache(size = options.l2_size,
76 assoc = options.l2_assoc)
77
78 cpu_seq = RubySequencer(version = i,
79 icache = l1i_cache,
80 dcache = l1d_cache,
81 physMemPort = phys_mem.port,
82 physmem = phys_mem)
83
84 if piobus != None:
85 cpu_seq.pio_port = piobus.port
86
87 l1_cntrl = L1Cache_Controller(version = i,
88 sequencer = cpu_seq,
89 L1IcacheMemory = l1i_cache,
90 L1DcacheMemory = l1d_cache,
91 L2cacheMemory = l2_cache)
92 #
93 # Add controllers and sequencers to the appropriate lists
94 #
95 cpu_sequencers.append(cpu_seq)
96 l1_cntrl_nodes.append(l1_cntrl)
97
98 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
99 mem_module_size = phys_mem_size / options.num_dirs
100
101 for i in xrange(options.num_dirs):
102 #
103 # Create the Ruby objects associated with the directory controller
104 #
105
106 mem_cntrl = RubyMemoryControl(version = i)
107
108 dir_size = MemorySize('0B')
109 dir_size.value = mem_module_size
110
111 dir_cntrl = Directory_Controller(version = i,
112 directory = \
113 RubyDirectoryMemory(version = i,
114 size = dir_size,
115 use_map = options.use_map,
116 map_levels = options.map_levels),
117 memBuffer = mem_cntrl)
118
119 dir_cntrl_nodes.append(dir_cntrl)
120
121 for i, dma_device in enumerate(dma_devices):
122 #
123 # Create the Ruby objects associated with the dma controller
124 #
125 dma_seq = DMASequencer(version = i,
126 physMemPort = phys_mem.port,
127 physmem = phys_mem)
128
129 dma_cntrl = DMA_Controller(version = i,
130 dma_sequencer = dma_seq)
131
132 dma_cntrl.dma_sequencer.port = dma_device.dma
133 dma_cntrl_nodes.append(dma_cntrl)
134
135 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
136
137 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
| 49def create_system(options, phys_mem, piobus, dma_devices):
50
51 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
52 panic("This script requires the MOESI_hammer protocol to be built.")
53
54 cpu_sequencers = []
55
56 #
57 # The ruby network creation expects the list of nodes in the system to be
58 # consistent with the NetDest list. Therefore the l1 controller nodes must be
59 # listed before the directory nodes and directory nodes before dma nodes, etc.
60 #
61 l1_cntrl_nodes = []
62 dir_cntrl_nodes = []
63 dma_cntrl_nodes = []
64
65 #
66 # Must create the individual controllers before the network to ensure the
67 # controller constructors are called before the network constructor
68 #
69
70 for i in xrange(options.num_cpus):
71 #
72 # First create the Ruby objects associated with this cpu
73 #
74 l1i_cache = L1Cache(size = options.l1i_size,
75 assoc = options.l1i_assoc)
76 l1d_cache = L1Cache(size = options.l1d_size,
77 assoc = options.l1d_assoc)
78 l2_cache = L2Cache(size = options.l2_size,
79 assoc = options.l2_assoc)
80
81 cpu_seq = RubySequencer(version = i,
82 icache = l1i_cache,
83 dcache = l1d_cache,
84 physMemPort = phys_mem.port,
85 physmem = phys_mem)
86
87 if piobus != None:
88 cpu_seq.pio_port = piobus.port
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 sequencer = cpu_seq,
92 L1IcacheMemory = l1i_cache,
93 L1DcacheMemory = l1d_cache,
94 L2cacheMemory = l2_cache)
95 #
96 # Add controllers and sequencers to the appropriate lists
97 #
98 cpu_sequencers.append(cpu_seq)
99 l1_cntrl_nodes.append(l1_cntrl)
100
101 phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
102 mem_module_size = phys_mem_size / options.num_dirs
103
104 for i in xrange(options.num_dirs):
105 #
106 # Create the Ruby objects associated with the directory controller
107 #
108
109 mem_cntrl = RubyMemoryControl(version = i)
110
111 dir_size = MemorySize('0B')
112 dir_size.value = mem_module_size
113
114 dir_cntrl = Directory_Controller(version = i,
115 directory = \
116 RubyDirectoryMemory(version = i,
117 size = dir_size,
118 use_map = options.use_map,
119 map_levels = options.map_levels),
120 memBuffer = mem_cntrl)
121
122 dir_cntrl_nodes.append(dir_cntrl)
123
124 for i, dma_device in enumerate(dma_devices):
125 #
126 # Create the Ruby objects associated with the dma controller
127 #
128 dma_seq = DMASequencer(version = i,
129 physMemPort = phys_mem.port,
130 physmem = phys_mem)
131
132 dma_cntrl = DMA_Controller(version = i,
133 dma_sequencer = dma_seq)
134
135 dma_cntrl.dma_sequencer.port = dma_device.dma
136 dma_cntrl_nodes.append(dma_cntrl)
137
138 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
139
140 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|