1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33from m5.util import addToPath
34
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33from m5.util import addToPath
34
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
|
40 assoc = 2
| |
41 latency = 3
| 40 latency = 3
|
42 size = 32768
| |
43
44#
45# Note: the L2 Cache latency is not currently used
46#
47class L2Cache(RubyCache):
| 41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
|
48 assoc = 16
| |
49 latency = 15
| 46 latency = 15
|
50 size = 1048576
| |
51
52def create_system(options, phys_mem, piobus, dma_devices):
53
54 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
55 panic("This script requires the MOESI_hammer protocol to be built.")
56
57 cpu_sequencers = []
58
59 #
60 # The ruby network creation expects the list of nodes in the system to be
61 # consistent with the NetDest list. Therefore the l1 controller nodes must be
62 # listed before the directory nodes and directory nodes before dma nodes, etc.
63 #
64 l1_cntrl_nodes = []
65 dir_cntrl_nodes = []
66 dma_cntrl_nodes = []
67
68 #
69 # Must create the individual controllers before the network to ensure the
70 # controller constructors are called before the network constructor
71 #
72
73 for i in xrange(options.num_cpus):
74 #
75 # First create the Ruby objects associated with this cpu
76 #
| 47
48def create_system(options, phys_mem, piobus, dma_devices):
49
50 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
51 panic("This script requires the MOESI_hammer protocol to be built.")
52
53 cpu_sequencers = []
54
55 #
56 # The ruby network creation expects the list of nodes in the system to be
57 # consistent with the NetDest list. Therefore the l1 controller nodes must be
58 # listed before the directory nodes and directory nodes before dma nodes, etc.
59 #
60 l1_cntrl_nodes = []
61 dir_cntrl_nodes = []
62 dma_cntrl_nodes = []
63
64 #
65 # Must create the individual controllers before the network to ensure the
66 # controller constructors are called before the network constructor
67 #
68
69 for i in xrange(options.num_cpus):
70 #
71 # First create the Ruby objects associated with this cpu
72 #
|
77 l1i_cache = L1Cache()
78 l1d_cache = L1Cache()
79 l2_cache = L2Cache()
| 73 l1i_cache = L1Cache(size = options.l1i_size,
74 assoc = options.l1i_assoc)
75 l1d_cache = L1Cache(size = options.l1d_size,
76 assoc = options.l1d_assoc)
77 l2_cache = L2Cache(size = options.l2_size,
78 assoc = options.l2_assoc)
|
80
81 cpu_seq = RubySequencer(icache = l1i_cache,
82 dcache = l1d_cache,
83 physMemPort = phys_mem.port,
84 physmem = phys_mem)
85
86 if piobus != None:
87 cpu_seq.pio_port = piobus.port
88
89 l1_cntrl = L1Cache_Controller(version = i,
90 sequencer = cpu_seq,
91 L1IcacheMemory = l1i_cache,
92 L1DcacheMemory = l1d_cache,
93 L2cacheMemory = l2_cache)
94 #
95 # Add controllers and sequencers to the appropriate lists
96 #
97 cpu_sequencers.append(cpu_seq)
98 l1_cntrl_nodes.append(l1_cntrl)
99
100 for i in xrange(options.num_dirs):
101 #
102 # Create the Ruby objects associated with the directory controller
103 #
104
105 mem_cntrl = RubyMemoryControl(version = i)
106
107 dir_cntrl = Directory_Controller(version = i,
108 directory = \
109 RubyDirectoryMemory(version = i),
110 memBuffer = mem_cntrl)
111
112 dir_cntrl_nodes.append(dir_cntrl)
113
114 for i, dma_device in enumerate(dma_devices):
115 #
116 # Create the Ruby objects associated with the dma controller
117 #
118 dma_seq = DMASequencer(version = i,
119 physMemPort = phys_mem.port,
120 physmem = phys_mem)
121
122 dma_cntrl = DMA_Controller(version = i,
123 dma_sequencer = dma_seq)
124
125 dma_cntrl.dma_sequencer.port = dma_device.dma
126 dma_cntrl_nodes.append(dma_cntrl)
127
128 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
129
130 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
| 79
80 cpu_seq = RubySequencer(icache = l1i_cache,
81 dcache = l1d_cache,
82 physMemPort = phys_mem.port,
83 physmem = phys_mem)
84
85 if piobus != None:
86 cpu_seq.pio_port = piobus.port
87
88 l1_cntrl = L1Cache_Controller(version = i,
89 sequencer = cpu_seq,
90 L1IcacheMemory = l1i_cache,
91 L1DcacheMemory = l1d_cache,
92 L2cacheMemory = l2_cache)
93 #
94 # Add controllers and sequencers to the appropriate lists
95 #
96 cpu_sequencers.append(cpu_seq)
97 l1_cntrl_nodes.append(l1_cntrl)
98
99 for i in xrange(options.num_dirs):
100 #
101 # Create the Ruby objects associated with the directory controller
102 #
103
104 mem_cntrl = RubyMemoryControl(version = i)
105
106 dir_cntrl = Directory_Controller(version = i,
107 directory = \
108 RubyDirectoryMemory(version = i),
109 memBuffer = mem_cntrl)
110
111 dir_cntrl_nodes.append(dir_cntrl)
112
113 for i, dma_device in enumerate(dma_devices):
114 #
115 # Create the Ruby objects associated with the dma controller
116 #
117 dma_seq = DMASequencer(version = i,
118 physMemPort = phys_mem.port,
119 physmem = phys_mem)
120
121 dma_cntrl = DMA_Controller(version = i,
122 dma_sequencer = dma_seq)
123
124 dma_cntrl.dma_sequencer.port = dma_device.dma
125 dma_cntrl_nodes.append(dma_cntrl)
126
127 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
128
129 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|