1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import m5 31from m5.objects import * 32from m5.defines import buildEnv 33from m5.util import addToPath 34 35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 assoc = 2 41 latency = 3 42 size = 32768 43 44# 45# Note: the L2 Cache latency is not currently used 46# 47class L2Cache(RubyCache): 48 assoc = 16 49 latency = 15 50 size = 1048576 51
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import m5 31from m5.objects import * 32from m5.defines import buildEnv 33from m5.util import addToPath 34 35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 assoc = 2 41 latency = 3 42 size = 32768 43 44# 45# Note: the L2 Cache latency is not currently used 46# 47class L2Cache(RubyCache): 48 assoc = 16 49 latency = 15 50 size = 1048576 51
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52def create_system(options, physmem):
| 52def create_system(options, phys_mem, piobus, dma_devices):
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53 54 if buildEnv['PROTOCOL'] != 'MOESI_hammer': 55 panic("This script requires the MOESI_hammer protocol to be built.") 56
| 53 54 if buildEnv['PROTOCOL'] != 'MOESI_hammer': 55 panic("This script requires the MOESI_hammer protocol to be built.") 56
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57 sequencers = []
| 57 cpu_sequencers = [] 58
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58 # 59 # The ruby network creation expects the list of nodes in the system to be 60 # consistent with the NetDest list. Therefore the l1 controller nodes must be 61 # listed before the directory nodes and directory nodes before dma nodes, etc. 62 # 63 l1_cntrl_nodes = [] 64 dir_cntrl_nodes = [] 65 dma_cntrl_nodes = [] 66 67 # 68 # Must create the individual controllers before the network to ensure the 69 # controller constructors are called before the network constructor 70 #
| 59 # 60 # The ruby network creation expects the list of nodes in the system to be 61 # consistent with the NetDest list. Therefore the l1 controller nodes must be 62 # listed before the directory nodes and directory nodes before dma nodes, etc. 63 # 64 l1_cntrl_nodes = [] 65 dir_cntrl_nodes = [] 66 dma_cntrl_nodes = [] 67 68 # 69 # Must create the individual controllers before the network to ensure the 70 # controller constructors are called before the network constructor 71 #
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71 for i in range(options.num_cpus):
| 72 73 for i in xrange(options.num_cpus):
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72 # 73 # First create the Ruby objects associated with this cpu
| 74 # 75 # First create the Ruby objects associated with this cpu
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74 # Eventually this code should go in a python file specific to the 75 # MOESI_hammer protocol
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76 # 77 l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i)) 78 l1i_cache = L1Cache(cache_profiler = l1i_profiler) 79 80 l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i)) 81 l1d_cache = L1Cache(cache_profiler = l1d_profiler) 82 83 l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i)) 84 l2_cache = L2Cache(cache_profiler = l2_profiler) 85 86 cpu_seq = RubySequencer(icache = l1i_cache, 87 dcache = l1d_cache,
| 76 # 77 l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i)) 78 l1i_cache = L1Cache(cache_profiler = l1i_profiler) 79 80 l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i)) 81 l1d_cache = L1Cache(cache_profiler = l1d_profiler) 82 83 l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i)) 84 l2_cache = L2Cache(cache_profiler = l2_profiler) 85 86 cpu_seq = RubySequencer(icache = l1i_cache, 87 dcache = l1d_cache,
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88 funcmem_port = physmem.port)
| 88 physMemPort = phys_mem.port, 89 physmem = phys_mem)
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89
| 90
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| 91 if piobus != None: 92 cpu_seq.pio_port = piobus.port 93
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90 l1_cntrl = L1Cache_Controller(version = i, 91 sequencer = cpu_seq, 92 L1IcacheMemory = l1i_cache, 93 L1DcacheMemory = l1d_cache, 94 L2cacheMemory = l2_cache)
| 94 l1_cntrl = L1Cache_Controller(version = i, 95 sequencer = cpu_seq, 96 L1IcacheMemory = l1i_cache, 97 L1DcacheMemory = l1d_cache, 98 L2cacheMemory = l2_cache)
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| 99 # 100 # Add controllers and sequencers to the appropriate lists 101 # 102 cpu_sequencers.append(cpu_seq) 103 l1_cntrl_nodes.append(l1_cntrl)
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95
| 104
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| 105 for i in xrange(options.num_dirs): 106 # 107 # Create the Ruby objects associated with the directory controller 108 # 109
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96 mem_cntrl = RubyMemoryControl(version = i) 97 98 dir_cntrl = Directory_Controller(version = i,
| 110 mem_cntrl = RubyMemoryControl(version = i) 111 112 dir_cntrl = Directory_Controller(version = i,
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99 directory = RubyDirectoryMemory(),
| 113 directory = \ 114 RubyDirectoryMemory(version = i),
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100 memBuffer = mem_cntrl) 101
| 115 memBuffer = mem_cntrl) 116
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102 dma_cntrl = DMA_Controller(version = i, 103 dma_sequencer = DMASequencer())
| 117 dir_cntrl_nodes.append(dir_cntrl)
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104
| 118
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| 119 for i, dma_device in enumerate(dma_devices):
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105 #
| 120 #
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106 # Add controllers and sequencers to the appropriate lists 107 # As noted above: Independent list are track to maintain the order of 108 # nodes/controllers assumed by the ruby network
| 121 # Create the Ruby objects associated with the dma controller
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109 #
| 122 #
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110 sequencers.append(cpu_seq) 111 l1_cntrl_nodes.append(l1_cntrl) 112 dir_cntrl_nodes.append(dir_cntrl)
| 123 dma_seq = DMASequencer(version = i, 124 physMemPort = phys_mem.port, 125 physmem = phys_mem) 126 127 dma_cntrl = DMA_Controller(version = i, 128 dma_sequencer = dma_seq) 129 130 dma_cntrl.dma_sequencer.port = dma_device.dma
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113 dma_cntrl_nodes.append(dma_cntrl) 114 115 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 116
| 131 dma_cntrl_nodes.append(dma_cntrl) 132 133 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 134
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117 return (sequencers, dir_cntrl_nodes, all_cntrls)
| 135 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
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| |