1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 2
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 10
47
48#
49# Probe filter is a cache, latency is not used
50#
51class ProbeFilter(RubyCache):
52 latency = 1
53
54def define_options(parser):
55 parser.add_option("--allow-atomic-migration", action="store_true",
56 help="allow migratory sharing for atomic only accessed blocks")
57 parser.add_option("--pf-on", action="store_true",
58 help="Hammer: enable Probe Filter")
59 parser.add_option("--dir-on", action="store_true",
60 help="Hammer: enable Full-bit Directory")
61
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 2
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 10
47
48#
49# Probe filter is a cache, latency is not used
50#
51class ProbeFilter(RubyCache):
52 latency = 1
53
54def define_options(parser):
55 parser.add_option("--allow-atomic-migration", action="store_true",
56 help="allow migratory sharing for atomic only accessed blocks")
57 parser.add_option("--pf-on", action="store_true",
58 help="Hammer: enable Probe Filter")
59 parser.add_option("--dir-on", action="store_true",
60 help="Hammer: enable Full-bit Directory")
61
|
62def create_system(options, system, piobus, dma_ports, ruby_system):
| 62def create_system(options, system, dma_ports, ruby_system):
|
63
64 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
65 panic("This script requires the MOESI_hammer protocol to be built.")
66
67 cpu_sequencers = []
68
69 #
70 # The ruby network creation expects the list of nodes in the system to be
71 # consistent with the NetDest list. Therefore the l1 controller nodes must be
72 # listed before the directory nodes and directory nodes before dma nodes, etc.
73 #
74 l1_cntrl_nodes = []
75 dir_cntrl_nodes = []
76 dma_cntrl_nodes = []
77
78 #
79 # Must create the individual controllers before the network to ensure the
80 # controller constructors are called before the network constructor
81 #
82 block_size_bits = int(math.log(options.cacheline_size, 2))
83
84 for i in xrange(options.num_cpus):
85 #
86 # First create the Ruby objects associated with this cpu
87 #
88 l1i_cache = L1Cache(size = options.l1i_size,
89 assoc = options.l1i_assoc,
90 start_index_bit = block_size_bits,
91 is_icache = True)
92 l1d_cache = L1Cache(size = options.l1d_size,
93 assoc = options.l1d_assoc,
94 start_index_bit = block_size_bits)
95 l2_cache = L2Cache(size = options.l2_size,
96 assoc = options.l2_assoc,
97 start_index_bit = block_size_bits)
98
99 l1_cntrl = L1Cache_Controller(version = i,
100 L1Icache = l1i_cache,
101 L1Dcache = l1d_cache,
102 L2cache = l2_cache,
103 no_mig_atomic = not \
104 options.allow_atomic_migration,
105 send_evictions = (
106 options.cpu_type == "detailed"),
107 transitions_per_cycle = options.ports,
108 ruby_system = ruby_system)
109
110 cpu_seq = RubySequencer(version = i,
111 icache = l1i_cache,
112 dcache = l1d_cache,
113 ruby_system = ruby_system)
114
115 l1_cntrl.sequencer = cpu_seq
| 63
64 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
65 panic("This script requires the MOESI_hammer protocol to be built.")
66
67 cpu_sequencers = []
68
69 #
70 # The ruby network creation expects the list of nodes in the system to be
71 # consistent with the NetDest list. Therefore the l1 controller nodes must be
72 # listed before the directory nodes and directory nodes before dma nodes, etc.
73 #
74 l1_cntrl_nodes = []
75 dir_cntrl_nodes = []
76 dma_cntrl_nodes = []
77
78 #
79 # Must create the individual controllers before the network to ensure the
80 # controller constructors are called before the network constructor
81 #
82 block_size_bits = int(math.log(options.cacheline_size, 2))
83
84 for i in xrange(options.num_cpus):
85 #
86 # First create the Ruby objects associated with this cpu
87 #
88 l1i_cache = L1Cache(size = options.l1i_size,
89 assoc = options.l1i_assoc,
90 start_index_bit = block_size_bits,
91 is_icache = True)
92 l1d_cache = L1Cache(size = options.l1d_size,
93 assoc = options.l1d_assoc,
94 start_index_bit = block_size_bits)
95 l2_cache = L2Cache(size = options.l2_size,
96 assoc = options.l2_assoc,
97 start_index_bit = block_size_bits)
98
99 l1_cntrl = L1Cache_Controller(version = i,
100 L1Icache = l1i_cache,
101 L1Dcache = l1d_cache,
102 L2cache = l2_cache,
103 no_mig_atomic = not \
104 options.allow_atomic_migration,
105 send_evictions = (
106 options.cpu_type == "detailed"),
107 transitions_per_cycle = options.ports,
108 ruby_system = ruby_system)
109
110 cpu_seq = RubySequencer(version = i,
111 icache = l1i_cache,
112 dcache = l1d_cache,
113 ruby_system = ruby_system)
114
115 l1_cntrl.sequencer = cpu_seq
|
116
117 if piobus != None:
118 cpu_seq.pio_master_port = piobus.slave
119 cpu_seq.mem_master_port = piobus.slave
120 cpu_seq.pio_slave_port = piobus.master
121
| |
122 if options.recycle_latency:
123 l1_cntrl.recycle_latency = options.recycle_latency
124
125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
126 #
127 # Add controllers and sequencers to the appropriate lists
128 #
129 cpu_sequencers.append(cpu_seq)
130 l1_cntrl_nodes.append(l1_cntrl)
131
132 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
133 assert(phys_mem_size % options.num_dirs == 0)
134 mem_module_size = phys_mem_size / options.num_dirs
135
136 #
137 # determine size and index bits for probe filter
138 # By default, the probe filter size is configured to be twice the
139 # size of the L2 cache.
140 #
141 pf_size = MemorySize(options.l2_size)
142 pf_size.value = pf_size.value * 2
143 dir_bits = int(math.log(options.num_dirs, 2))
144 pf_bits = int(math.log(pf_size.value, 2))
145 if options.numa_high_bit:
146 if options.pf_on or options.dir_on:
147 # if numa high bit explicitly set, make sure it does not overlap
148 # with the probe filter index
149 assert(options.numa_high_bit - dir_bits > pf_bits)
150
151 # set the probe filter start bit to just above the block offset
152 pf_start_bit = block_size_bits
153 else:
154 if dir_bits > 0:
155 pf_start_bit = dir_bits + block_size_bits - 1
156 else:
157 pf_start_bit = block_size_bits
158
159 # Run each of the ruby memory controllers at a ratio of the frequency of
160 # the ruby system
161 # clk_divider value is a fix to pass regression.
162 ruby_system.memctrl_clk_domain = DerivedClockDomain(
163 clk_domain=ruby_system.clk_domain,
164 clk_divider=3)
165
166 for i in xrange(options.num_dirs):
167 #
168 # Create the Ruby objects associated with the directory controller
169 #
170
171 mem_cntrl = RubyMemoryControl(
172 clk_domain = ruby_system.memctrl_clk_domain,
173 version = i,
174 ruby_system = ruby_system)
175
176 dir_size = MemorySize('0B')
177 dir_size.value = mem_module_size
178
179 pf = ProbeFilter(size = pf_size, assoc = 4,
180 start_index_bit = pf_start_bit)
181
182 dir_cntrl = Directory_Controller(version = i,
183 directory = \
184 RubyDirectoryMemory( \
185 version = i,
186 size = dir_size,
187 use_map = options.use_map,
188 map_levels = \
189 options.map_levels,
190 numa_high_bit = \
191 options.numa_high_bit),
192 probeFilter = pf,
193 memBuffer = mem_cntrl,
194 probe_filter_enabled = options.pf_on,
195 full_bit_dir_enabled = options.dir_on,
196 transitions_per_cycle = options.ports,
197 ruby_system = ruby_system)
198
199 if options.recycle_latency:
200 dir_cntrl.recycle_latency = options.recycle_latency
201
202 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
203 dir_cntrl_nodes.append(dir_cntrl)
204
205 for i, dma_port in enumerate(dma_ports):
206 #
207 # Create the Ruby objects associated with the dma controller
208 #
209 dma_seq = DMASequencer(version = i,
210 ruby_system = ruby_system)
211
212 dma_cntrl = DMA_Controller(version = i,
213 dma_sequencer = dma_seq,
214 transitions_per_cycle = options.ports,
215 ruby_system = ruby_system)
216
217 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
218 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
219 dma_cntrl_nodes.append(dma_cntrl)
220
221 if options.recycle_latency:
222 dma_cntrl.recycle_latency = options.recycle_latency
223
224 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
225 topology = create_topology(all_cntrls, options)
226
227 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 116 if options.recycle_latency:
117 l1_cntrl.recycle_latency = options.recycle_latency
118
119 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
120 #
121 # Add controllers and sequencers to the appropriate lists
122 #
123 cpu_sequencers.append(cpu_seq)
124 l1_cntrl_nodes.append(l1_cntrl)
125
126 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
127 assert(phys_mem_size % options.num_dirs == 0)
128 mem_module_size = phys_mem_size / options.num_dirs
129
130 #
131 # determine size and index bits for probe filter
132 # By default, the probe filter size is configured to be twice the
133 # size of the L2 cache.
134 #
135 pf_size = MemorySize(options.l2_size)
136 pf_size.value = pf_size.value * 2
137 dir_bits = int(math.log(options.num_dirs, 2))
138 pf_bits = int(math.log(pf_size.value, 2))
139 if options.numa_high_bit:
140 if options.pf_on or options.dir_on:
141 # if numa high bit explicitly set, make sure it does not overlap
142 # with the probe filter index
143 assert(options.numa_high_bit - dir_bits > pf_bits)
144
145 # set the probe filter start bit to just above the block offset
146 pf_start_bit = block_size_bits
147 else:
148 if dir_bits > 0:
149 pf_start_bit = dir_bits + block_size_bits - 1
150 else:
151 pf_start_bit = block_size_bits
152
153 # Run each of the ruby memory controllers at a ratio of the frequency of
154 # the ruby system
155 # clk_divider value is a fix to pass regression.
156 ruby_system.memctrl_clk_domain = DerivedClockDomain(
157 clk_domain=ruby_system.clk_domain,
158 clk_divider=3)
159
160 for i in xrange(options.num_dirs):
161 #
162 # Create the Ruby objects associated with the directory controller
163 #
164
165 mem_cntrl = RubyMemoryControl(
166 clk_domain = ruby_system.memctrl_clk_domain,
167 version = i,
168 ruby_system = ruby_system)
169
170 dir_size = MemorySize('0B')
171 dir_size.value = mem_module_size
172
173 pf = ProbeFilter(size = pf_size, assoc = 4,
174 start_index_bit = pf_start_bit)
175
176 dir_cntrl = Directory_Controller(version = i,
177 directory = \
178 RubyDirectoryMemory( \
179 version = i,
180 size = dir_size,
181 use_map = options.use_map,
182 map_levels = \
183 options.map_levels,
184 numa_high_bit = \
185 options.numa_high_bit),
186 probeFilter = pf,
187 memBuffer = mem_cntrl,
188 probe_filter_enabled = options.pf_on,
189 full_bit_dir_enabled = options.dir_on,
190 transitions_per_cycle = options.ports,
191 ruby_system = ruby_system)
192
193 if options.recycle_latency:
194 dir_cntrl.recycle_latency = options.recycle_latency
195
196 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
197 dir_cntrl_nodes.append(dir_cntrl)
198
199 for i, dma_port in enumerate(dma_ports):
200 #
201 # Create the Ruby objects associated with the dma controller
202 #
203 dma_seq = DMASequencer(version = i,
204 ruby_system = ruby_system)
205
206 dma_cntrl = DMA_Controller(version = i,
207 dma_sequencer = dma_seq,
208 transitions_per_cycle = options.ports,
209 ruby_system = ruby_system)
210
211 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
212 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
213 dma_cntrl_nodes.append(dma_cntrl)
214
215 if options.recycle_latency:
216 dma_cntrl.recycle_latency = options.recycle_latency
217
218 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
219 topology = create_topology(all_cntrls, options)
220
221 return (cpu_sequencers, dir_cntrl_nodes, topology)
|