1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 2
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 10
47
48#
49# Probe filter is a cache, latency is not used
50#
51class ProbeFilter(RubyCache):
52 latency = 1
53
54def define_options(parser):
55 parser.add_option("--allow-atomic-migration", action="store_true",
56 help="allow migratory sharing for atomic only accessed blocks")
57 parser.add_option("--pf-on", action="store_true",
58 help="Hammer: enable Probe Filter")
59 parser.add_option("--dir-on", action="store_true",
60 help="Hammer: enable Full-bit Directory")
61
62def create_system(options, system, piobus, dma_ports, ruby_system):
63
64 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
65 panic("This script requires the MOESI_hammer protocol to be built.")
66
67 cpu_sequencers = []
68
69 #
70 # The ruby network creation expects the list of nodes in the system to be
71 # consistent with the NetDest list. Therefore the l1 controller nodes must be
72 # listed before the directory nodes and directory nodes before dma nodes, etc.
73 #
74 l1_cntrl_nodes = []
75 dir_cntrl_nodes = []
76 dma_cntrl_nodes = []
77
78 #
79 # Must create the individual controllers before the network to ensure the
80 # controller constructors are called before the network constructor
81 #
82 block_size_bits = int(math.log(options.cacheline_size, 2))
83
84 for i in xrange(options.num_cpus):
85 #
86 # First create the Ruby objects associated with this cpu
87 #
88 l1i_cache = L1Cache(size = options.l1i_size,
89 assoc = options.l1i_assoc,
90 start_index_bit = block_size_bits,
91 is_icache = True)
92 l1d_cache = L1Cache(size = options.l1d_size,
93 assoc = options.l1d_assoc,
94 start_index_bit = block_size_bits)
95 l2_cache = L2Cache(size = options.l2_size,
96 assoc = options.l2_assoc,
97 start_index_bit = block_size_bits)
98
99 l1_cntrl = L1Cache_Controller(version = i,
100 L1Icache = l1i_cache,
101 L1Dcache = l1d_cache,
102 L2cache = l2_cache,
103 no_mig_atomic = not \
104 options.allow_atomic_migration,
105 send_evictions = (
106 options.cpu_type == "detailed"),
107 transitions_per_cycle = options.ports,
108 ruby_system = ruby_system)
109
110 cpu_seq = RubySequencer(version = i,
111 icache = l1i_cache,
112 dcache = l1d_cache,
113 ruby_system = ruby_system)
114
115 l1_cntrl.sequencer = cpu_seq
116
117 if piobus != None:
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40 latency = 2
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46 latency = 10
47
48#
49# Probe filter is a cache, latency is not used
50#
51class ProbeFilter(RubyCache):
52 latency = 1
53
54def define_options(parser):
55 parser.add_option("--allow-atomic-migration", action="store_true",
56 help="allow migratory sharing for atomic only accessed blocks")
57 parser.add_option("--pf-on", action="store_true",
58 help="Hammer: enable Probe Filter")
59 parser.add_option("--dir-on", action="store_true",
60 help="Hammer: enable Full-bit Directory")
61
62def create_system(options, system, piobus, dma_ports, ruby_system):
63
64 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
65 panic("This script requires the MOESI_hammer protocol to be built.")
66
67 cpu_sequencers = []
68
69 #
70 # The ruby network creation expects the list of nodes in the system to be
71 # consistent with the NetDest list. Therefore the l1 controller nodes must be
72 # listed before the directory nodes and directory nodes before dma nodes, etc.
73 #
74 l1_cntrl_nodes = []
75 dir_cntrl_nodes = []
76 dma_cntrl_nodes = []
77
78 #
79 # Must create the individual controllers before the network to ensure the
80 # controller constructors are called before the network constructor
81 #
82 block_size_bits = int(math.log(options.cacheline_size, 2))
83
84 for i in xrange(options.num_cpus):
85 #
86 # First create the Ruby objects associated with this cpu
87 #
88 l1i_cache = L1Cache(size = options.l1i_size,
89 assoc = options.l1i_assoc,
90 start_index_bit = block_size_bits,
91 is_icache = True)
92 l1d_cache = L1Cache(size = options.l1d_size,
93 assoc = options.l1d_assoc,
94 start_index_bit = block_size_bits)
95 l2_cache = L2Cache(size = options.l2_size,
96 assoc = options.l2_assoc,
97 start_index_bit = block_size_bits)
98
99 l1_cntrl = L1Cache_Controller(version = i,
100 L1Icache = l1i_cache,
101 L1Dcache = l1d_cache,
102 L2cache = l2_cache,
103 no_mig_atomic = not \
104 options.allow_atomic_migration,
105 send_evictions = (
106 options.cpu_type == "detailed"),
107 transitions_per_cycle = options.ports,
108 ruby_system = ruby_system)
109
110 cpu_seq = RubySequencer(version = i,
111 icache = l1i_cache,
112 dcache = l1d_cache,
113 ruby_system = ruby_system)
114
115 l1_cntrl.sequencer = cpu_seq
116
117 if piobus != None:
|
119
120 if options.recycle_latency:
121 l1_cntrl.recycle_latency = options.recycle_latency
122
123 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
124 #
125 # Add controllers and sequencers to the appropriate lists
126 #
127 cpu_sequencers.append(cpu_seq)
128 l1_cntrl_nodes.append(l1_cntrl)
129
130 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
131 assert(phys_mem_size % options.num_dirs == 0)
132 mem_module_size = phys_mem_size / options.num_dirs
133
134 #
135 # determine size and index bits for probe filter
136 # By default, the probe filter size is configured to be twice the
137 # size of the L2 cache.
138 #
139 pf_size = MemorySize(options.l2_size)
140 pf_size.value = pf_size.value * 2
141 dir_bits = int(math.log(options.num_dirs, 2))
142 pf_bits = int(math.log(pf_size.value, 2))
143 if options.numa_high_bit:
144 if options.pf_on or options.dir_on:
145 # if numa high bit explicitly set, make sure it does not overlap
146 # with the probe filter index
147 assert(options.numa_high_bit - dir_bits > pf_bits)
148
149 # set the probe filter start bit to just above the block offset
150 pf_start_bit = block_size_bits
151 else:
152 if dir_bits > 0:
153 pf_start_bit = dir_bits + block_size_bits - 1
154 else:
155 pf_start_bit = block_size_bits
156
157 # Run each of the ruby memory controllers at a ratio of the frequency of
158 # the ruby system
159 # clk_divider value is a fix to pass regression.
160 ruby_system.memctrl_clk_domain = DerivedClockDomain(
161 clk_domain=ruby_system.clk_domain,
162 clk_divider=3)
163
164 for i in xrange(options.num_dirs):
165 #
166 # Create the Ruby objects associated with the directory controller
167 #
168
169 mem_cntrl = RubyMemoryControl(
170 clk_domain = ruby_system.memctrl_clk_domain,
171 version = i,
172 ruby_system = ruby_system)
173
174 dir_size = MemorySize('0B')
175 dir_size.value = mem_module_size
176
177 pf = ProbeFilter(size = pf_size, assoc = 4,
178 start_index_bit = pf_start_bit)
179
180 dir_cntrl = Directory_Controller(version = i,
181 directory = \
182 RubyDirectoryMemory( \
183 version = i,
184 size = dir_size,
185 use_map = options.use_map,
186 map_levels = \
187 options.map_levels,
188 numa_high_bit = \
189 options.numa_high_bit),
190 probeFilter = pf,
191 memBuffer = mem_cntrl,
192 probe_filter_enabled = options.pf_on,
193 full_bit_dir_enabled = options.dir_on,
194 transitions_per_cycle = options.ports,
195 ruby_system = ruby_system)
196
197 if options.recycle_latency:
198 dir_cntrl.recycle_latency = options.recycle_latency
199
200 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
201 dir_cntrl_nodes.append(dir_cntrl)
202
203 for i, dma_port in enumerate(dma_ports):
204 #
205 # Create the Ruby objects associated with the dma controller
206 #
207 dma_seq = DMASequencer(version = i,
208 ruby_system = ruby_system)
209
210 dma_cntrl = DMA_Controller(version = i,
211 dma_sequencer = dma_seq,
212 transitions_per_cycle = options.ports,
213 ruby_system = ruby_system)
214
215 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
216 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
217 dma_cntrl_nodes.append(dma_cntrl)
218
219 if options.recycle_latency:
220 dma_cntrl.recycle_latency = options.recycle_latency
221
222 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
223 topology = create_topology(all_cntrls, options)
224
225 return (cpu_sequencers, dir_cntrl_nodes, topology)
| 121
122 if options.recycle_latency:
123 l1_cntrl.recycle_latency = options.recycle_latency
124
125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
126 #
127 # Add controllers and sequencers to the appropriate lists
128 #
129 cpu_sequencers.append(cpu_seq)
130 l1_cntrl_nodes.append(l1_cntrl)
131
132 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
133 assert(phys_mem_size % options.num_dirs == 0)
134 mem_module_size = phys_mem_size / options.num_dirs
135
136 #
137 # determine size and index bits for probe filter
138 # By default, the probe filter size is configured to be twice the
139 # size of the L2 cache.
140 #
141 pf_size = MemorySize(options.l2_size)
142 pf_size.value = pf_size.value * 2
143 dir_bits = int(math.log(options.num_dirs, 2))
144 pf_bits = int(math.log(pf_size.value, 2))
145 if options.numa_high_bit:
146 if options.pf_on or options.dir_on:
147 # if numa high bit explicitly set, make sure it does not overlap
148 # with the probe filter index
149 assert(options.numa_high_bit - dir_bits > pf_bits)
150
151 # set the probe filter start bit to just above the block offset
152 pf_start_bit = block_size_bits
153 else:
154 if dir_bits > 0:
155 pf_start_bit = dir_bits + block_size_bits - 1
156 else:
157 pf_start_bit = block_size_bits
158
159 # Run each of the ruby memory controllers at a ratio of the frequency of
160 # the ruby system
161 # clk_divider value is a fix to pass regression.
162 ruby_system.memctrl_clk_domain = DerivedClockDomain(
163 clk_domain=ruby_system.clk_domain,
164 clk_divider=3)
165
166 for i in xrange(options.num_dirs):
167 #
168 # Create the Ruby objects associated with the directory controller
169 #
170
171 mem_cntrl = RubyMemoryControl(
172 clk_domain = ruby_system.memctrl_clk_domain,
173 version = i,
174 ruby_system = ruby_system)
175
176 dir_size = MemorySize('0B')
177 dir_size.value = mem_module_size
178
179 pf = ProbeFilter(size = pf_size, assoc = 4,
180 start_index_bit = pf_start_bit)
181
182 dir_cntrl = Directory_Controller(version = i,
183 directory = \
184 RubyDirectoryMemory( \
185 version = i,
186 size = dir_size,
187 use_map = options.use_map,
188 map_levels = \
189 options.map_levels,
190 numa_high_bit = \
191 options.numa_high_bit),
192 probeFilter = pf,
193 memBuffer = mem_cntrl,
194 probe_filter_enabled = options.pf_on,
195 full_bit_dir_enabled = options.dir_on,
196 transitions_per_cycle = options.ports,
197 ruby_system = ruby_system)
198
199 if options.recycle_latency:
200 dir_cntrl.recycle_latency = options.recycle_latency
201
202 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
203 dir_cntrl_nodes.append(dir_cntrl)
204
205 for i, dma_port in enumerate(dma_ports):
206 #
207 # Create the Ruby objects associated with the dma controller
208 #
209 dma_seq = DMASequencer(version = i,
210 ruby_system = ruby_system)
211
212 dma_cntrl = DMA_Controller(version = i,
213 dma_sequencer = dma_seq,
214 transitions_per_cycle = options.ports,
215 ruby_system = ruby_system)
216
217 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
218 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
219 dma_cntrl_nodes.append(dma_cntrl)
220
221 if options.recycle_latency:
222 dma_cntrl.recycle_latency = options.recycle_latency
223
224 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
225 topology = create_topology(all_cntrls, options)
226
227 return (cpu_sequencers, dir_cntrl_nodes, topology)
|