MOESI_hammer.py (9826:014ff1fbff6d) | MOESI_hammer.py (9841:69c158420c51) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 cntrl_id = cntrl_count, 103 L1Icache = l1i_cache, 104 L1Dcache = l1d_cache, 105 L2cache = l2_cache, 106 no_mig_atomic = not \ 107 options.allow_atomic_migration, 108 send_evictions = ( 109 options.cpu_type == "detailed"), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 93 unchanged lines hidden (view full) --- 102 cntrl_id = cntrl_count, 103 L1Icache = l1i_cache, 104 L1Dcache = l1d_cache, 105 L2cache = l2_cache, 106 no_mig_atomic = not \ 107 options.allow_atomic_migration, 108 send_evictions = ( 109 options.cpu_type == "detailed"), |
110 transitions_per_cycle = options.ports, |
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110 ruby_system = ruby_system) 111 112 cpu_seq = RubySequencer(version = i, 113 icache = l1i_cache, 114 dcache = l1d_cache, 115 ruby_system = ruby_system) 116 117 l1_cntrl.sequencer = cpu_seq --- 73 unchanged lines hidden (view full) --- 191 map_levels = \ 192 options.map_levels, 193 numa_high_bit = \ 194 options.numa_high_bit), 195 probeFilter = pf, 196 memBuffer = mem_cntrl, 197 probe_filter_enabled = options.pf_on, 198 full_bit_dir_enabled = options.dir_on, | 111 ruby_system = ruby_system) 112 113 cpu_seq = RubySequencer(version = i, 114 icache = l1i_cache, 115 dcache = l1d_cache, 116 ruby_system = ruby_system) 117 118 l1_cntrl.sequencer = cpu_seq --- 73 unchanged lines hidden (view full) --- 192 map_levels = \ 193 options.map_levels, 194 numa_high_bit = \ 195 options.numa_high_bit), 196 probeFilter = pf, 197 memBuffer = mem_cntrl, 198 probe_filter_enabled = options.pf_on, 199 full_bit_dir_enabled = options.dir_on, |
200 transitions_per_cycle = options.ports, |
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199 ruby_system = ruby_system) 200 201 if options.recycle_latency: 202 dir_cntrl.recycle_latency = options.recycle_latency 203 204 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 205 dir_cntrl_nodes.append(dir_cntrl) 206 --- 4 unchanged lines hidden (view full) --- 211 # Create the Ruby objects associated with the dma controller 212 # 213 dma_seq = DMASequencer(version = i, 214 ruby_system = ruby_system) 215 216 dma_cntrl = DMA_Controller(version = i, 217 cntrl_id = cntrl_count, 218 dma_sequencer = dma_seq, | 201 ruby_system = ruby_system) 202 203 if options.recycle_latency: 204 dir_cntrl.recycle_latency = options.recycle_latency 205 206 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 207 dir_cntrl_nodes.append(dir_cntrl) 208 --- 4 unchanged lines hidden (view full) --- 213 # Create the Ruby objects associated with the dma controller 214 # 215 dma_seq = DMASequencer(version = i, 216 ruby_system = ruby_system) 217 218 dma_cntrl = DMA_Controller(version = i, 219 cntrl_id = cntrl_count, 220 dma_sequencer = dma_seq, |
221 transitions_per_cycle = options.ports, |
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219 ruby_system = ruby_system) 220 221 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 222 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 223 dma_cntrl_nodes.append(dma_cntrl) 224 225 if options.recycle_latency: 226 dma_cntrl.recycle_latency = options.recycle_latency 227 228 cntrl_count += 1 229 230 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 231 232 topology = create_topology(all_cntrls, options) 233 234 return (cpu_sequencers, dir_cntrl_nodes, topology) | 222 ruby_system = ruby_system) 223 224 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 225 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 226 dma_cntrl_nodes.append(dma_cntrl) 227 228 if options.recycle_latency: 229 dma_cntrl.recycle_latency = options.recycle_latency 230 231 cntrl_count += 1 232 233 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 234 235 topology = create_topology(all_cntrls, options) 236 237 return (cpu_sequencers, dir_cntrl_nodes, topology) |