MOESI_hammer.py (8717:5c253f1031d7) | MOESI_hammer.py (8845:a230379caf65) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 104 unchanged lines hidden (view full) --- 113 dcache = l1d_cache, 114 physMemPort = system.physmem.port, 115 physmem = system.physmem, 116 ruby_system = ruby_system) 117 118 l1_cntrl.sequencer = cpu_seq 119 120 if piobus != None: | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 104 unchanged lines hidden (view full) --- 113 dcache = l1d_cache, 114 physMemPort = system.physmem.port, 115 physmem = system.physmem, 116 ruby_system = ruby_system) 117 118 l1_cntrl.sequencer = cpu_seq 119 120 if piobus != None: |
121 cpu_seq.pio_port = piobus.port | 121 cpu_seq.pio_port = piobus.slave |
122 123 if options.recycle_latency: 124 l1_cntrl.recycle_latency = options.recycle_latency 125 126 exec("system.l1_cntrl%d = l1_cntrl" % i) 127 # 128 # Add controllers and sequencers to the appropriate lists 129 # --- 78 unchanged lines hidden (view full) --- 208 209 dma_cntrl = DMA_Controller(version = i, 210 cntrl_id = cntrl_count, 211 dma_sequencer = dma_seq, 212 ruby_system = ruby_system) 213 214 exec("system.dma_cntrl%d = dma_cntrl" % i) 215 if dma_device.type == 'MemTest': | 122 123 if options.recycle_latency: 124 l1_cntrl.recycle_latency = options.recycle_latency 125 126 exec("system.l1_cntrl%d = l1_cntrl" % i) 127 # 128 # Add controllers and sequencers to the appropriate lists 129 # --- 78 unchanged lines hidden (view full) --- 208 209 dma_cntrl = DMA_Controller(version = i, 210 cntrl_id = cntrl_count, 211 dma_sequencer = dma_seq, 212 ruby_system = ruby_system) 213 214 exec("system.dma_cntrl%d = dma_cntrl" % i) 215 if dma_device.type == 'MemTest': |
216 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) | 216 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i) |
217 else: | 217 else: |
218 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) | 218 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i) |
219 dma_cntrl_nodes.append(dma_cntrl) 220 221 if options.recycle_latency: 222 dma_cntrl.recycle_latency = options.recycle_latency 223 224 cntrl_count += 1 225 226 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 227 228 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 219 dma_cntrl_nodes.append(dma_cntrl) 220 221 if options.recycle_latency: 222 dma_cntrl.recycle_latency = options.recycle_latency 223 224 cntrl_count += 1 225 226 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 227 228 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |