MOESI_hammer.py (7564:3559d47839a1) | MOESI_hammer.py (7566:6919df046bba) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 91 unchanged lines hidden (view full) --- 100 l1_cntrl = L1Cache_Controller(version = i, 101 sequencer = cpu_seq, 102 L1IcacheMemory = l1i_cache, 103 L1DcacheMemory = l1d_cache, 104 L2cacheMemory = l2_cache, 105 no_mig_atomic = not \ 106 options.allow_atomic_migration) 107 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 91 unchanged lines hidden (view full) --- 100 l1_cntrl = L1Cache_Controller(version = i, 101 sequencer = cpu_seq, 102 L1IcacheMemory = l1i_cache, 103 L1DcacheMemory = l1d_cache, 104 L2cacheMemory = l2_cache, 105 no_mig_atomic = not \ 106 options.allow_atomic_migration) 107 |
108 if options.recycle_latency: 109 l1_cntrl.recycle_latency = options.recycle_latency 110 |
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108 exec("system.l1_cntrl%d = l1_cntrl" % i) 109 # 110 # Add controllers and sequencers to the appropriate lists 111 # 112 cpu_sequencers.append(cpu_seq) 113 l1_cntrl_nodes.append(l1_cntrl) 114 115 phys_mem_size = long(system.physmem.range.second) - \ --- 43 unchanged lines hidden (view full) --- 159 use_map = options.use_map, 160 map_levels = \ 161 options.map_levels), 162 probeFilter = pf, 163 memBuffer = mem_cntrl, 164 probe_filter_enabled = \ 165 options.pf_on) 166 | 111 exec("system.l1_cntrl%d = l1_cntrl" % i) 112 # 113 # Add controllers and sequencers to the appropriate lists 114 # 115 cpu_sequencers.append(cpu_seq) 116 l1_cntrl_nodes.append(l1_cntrl) 117 118 phys_mem_size = long(system.physmem.range.second) - \ --- 43 unchanged lines hidden (view full) --- 162 use_map = options.use_map, 163 map_levels = \ 164 options.map_levels), 165 probeFilter = pf, 166 memBuffer = mem_cntrl, 167 probe_filter_enabled = \ 168 options.pf_on) 169 |
170 if options.recycle_latency: 171 dir_cntrl.recycle_latency = options.recycle_latency 172 |
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167 exec("system.dir_cntrl%d = dir_cntrl" % i) 168 dir_cntrl_nodes.append(dir_cntrl) 169 170 for i, dma_device in enumerate(dma_devices): 171 # 172 # Create the Ruby objects associated with the dma controller 173 # 174 dma_seq = DMASequencer(version = i, --- 6 unchanged lines hidden (view full) --- 181 exec("system.dma_cntrl%d = dma_cntrl" % i) 182 if dma_device.type == 'MemTest': 183 system.dma_cntrl.dma_sequencer.port = dma_device.test 184 else: 185 system.dma_cntrl.dma_sequencer.port = dma_device.dma 186 dma_cntrl.dma_sequencer.port = dma_device.dma 187 dma_cntrl_nodes.append(dma_cntrl) 188 | 173 exec("system.dir_cntrl%d = dir_cntrl" % i) 174 dir_cntrl_nodes.append(dir_cntrl) 175 176 for i, dma_device in enumerate(dma_devices): 177 # 178 # Create the Ruby objects associated with the dma controller 179 # 180 dma_seq = DMASequencer(version = i, --- 6 unchanged lines hidden (view full) --- 187 exec("system.dma_cntrl%d = dma_cntrl" % i) 188 if dma_device.type == 'MemTest': 189 system.dma_cntrl.dma_sequencer.port = dma_device.test 190 else: 191 system.dma_cntrl.dma_sequencer.port = dma_device.dma 192 dma_cntrl.dma_sequencer.port = dma_device.dma 193 dma_cntrl_nodes.append(dma_cntrl) 194 |
195 if options.recycle_latency: 196 dma_cntrl.recycle_latency = options.recycle_latency 197 |
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189 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 190 191 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) | 198 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 199 200 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |