1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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100 l1_cntrl = L1Cache_Controller(version = i,
101 sequencer = cpu_seq,
102 L1IcacheMemory = l1i_cache,
103 L1DcacheMemory = l1d_cache,
104 L2cacheMemory = l2_cache,
105 no_mig_atomic = not \
106 options.allow_atomic_migration)
107
108 exec("system.l1_cntrl%d = l1_cntrl" % i)
109 #
110 # Add controllers and sequencers to the appropriate lists
111 #
112 cpu_sequencers.append(cpu_seq)
113 l1_cntrl_nodes.append(l1_cntrl)
114
115 phys_mem_size = long(system.physmem.range.second) - \

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159 use_map = options.use_map,
160 map_levels = \
161 options.map_levels),
162 probeFilter = pf,
163 memBuffer = mem_cntrl,
164 probe_filter_enabled = \
165 options.pf_on)
166
167 exec("system.dir_cntrl%d = dir_cntrl" % i)
168 dir_cntrl_nodes.append(dir_cntrl)
169
170 for i, dma_device in enumerate(dma_devices):
171 #
172 # Create the Ruby objects associated with the dma controller
173 #
174 dma_seq = DMASequencer(version = i,

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181 exec("system.dma_cntrl%d = dma_cntrl" % i)
182 if dma_device.type == 'MemTest':
183 system.dma_cntrl.dma_sequencer.port = dma_device.test
184 else:
185 system.dma_cntrl.dma_sequencer.port = dma_device.dma
186 dma_cntrl.dma_sequencer.port = dma_device.dma
187 dma_cntrl_nodes.append(dma_cntrl)
188
189 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
190
191 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)