1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 13 unchanged lines hidden (view full) ---

22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33
34#
35# Note: the L1 Cache latency is only used by the sequencer on fast path hits
36#
37class L1Cache(RubyCache):
38 latency = 2
39
40#
41# Note: the L2 Cache latency is not currently used
42#
43class L2Cache(RubyCache):
44 latency = 10
45
46def define_options(parser):
47 parser.add_option("--allow-atomic-migration", action="store_true",
48 help="allow migratory sharing for atomic only accessed blocks")
49
50def create_system(options, system, piobus, dma_devices):
51
52 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
53 panic("This script requires the MOESI_hammer protocol to be built.")
54
55 cpu_sequencers = []
56
57 #

--- 44 unchanged lines hidden (view full) ---

102 #
103 cpu_sequencers.append(cpu_seq)
104 l1_cntrl_nodes.append(l1_cntrl)
105
106 phys_mem_size = long(system.physmem.range.second) - \
107 long(system.physmem.range.first) + 1
108 mem_module_size = phys_mem_size / options.num_dirs
109
110 for i in xrange(options.num_dirs):
111 #
112 # Create the Ruby objects associated with the directory controller
113 #
114
115 mem_cntrl = RubyMemoryControl(version = i)
116
117 dir_size = MemorySize('0B')
118 dir_size.value = mem_module_size
119
120 dir_cntrl = Directory_Controller(version = i,
121 directory = \
122 RubyDirectoryMemory( \
123 version = i,
124 size = dir_size,
125 use_map = options.use_map,
126 map_levels = \
127 options.map_levels),
128 memBuffer = mem_cntrl)
129
130 exec("system.dir_cntrl%d = dir_cntrl" % i)
131 dir_cntrl_nodes.append(dir_cntrl)
132
133 for i, dma_device in enumerate(dma_devices):
134 #
135 # Create the Ruby objects associated with the dma controller
136 #

--- 18 unchanged lines hidden ---