1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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44#
45# Note: the L2 Cache latency is not currently used
46#
47class L2Cache(RubyCache):
48 assoc = 16
49 latency = 15
50 size = 1048576
51
52def create_system(options, physmem):
53
54 if buildEnv['PROTOCOL'] != 'MOESI_hammer':
55 panic("This script requires the MOESI_hammer protocol to be built.")
56
57 sequencers = []
58 #
59 # The ruby network creation expects the list of nodes in the system to be
60 # consistent with the NetDest list. Therefore the l1 controller nodes must be
61 # listed before the directory nodes and directory nodes before dma nodes, etc.
62 #
63 l1_cntrl_nodes = []
64 dir_cntrl_nodes = []
65 dma_cntrl_nodes = []
66
67 #
68 # Must create the individual controllers before the network to ensure the
69 # controller constructors are called before the network constructor
70 #
71 for i in range(options.num_cpus):
72 #
73 # First create the Ruby objects associated with this cpu
74 # Eventually this code should go in a python file specific to the
75 # MOESI_hammer protocol
76 #
77 l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i))
78 l1i_cache = L1Cache(cache_profiler = l1i_profiler)
79
80 l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i))
81 l1d_cache = L1Cache(cache_profiler = l1d_profiler)
82
83 l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i))
84 l2_cache = L2Cache(cache_profiler = l2_profiler)
85
86 cpu_seq = RubySequencer(icache = l1i_cache,
87 dcache = l1d_cache,
88 funcmem_port = physmem.port)
89
90 l1_cntrl = L1Cache_Controller(version = i,
91 sequencer = cpu_seq,
92 L1IcacheMemory = l1i_cache,
93 L1DcacheMemory = l1d_cache,
94 L2cacheMemory = l2_cache)
95
96 mem_cntrl = RubyMemoryControl(version = i)
97
98 dir_cntrl = Directory_Controller(version = i,
99 directory = RubyDirectoryMemory(),
100 memBuffer = mem_cntrl)
101
102 dma_cntrl = DMA_Controller(version = i,
103 dma_sequencer = DMASequencer())
104
105 #
106 # Add controllers and sequencers to the appropriate lists
107 # As noted above: Independent list are track to maintain the order of
108 # nodes/controllers assumed by the ruby network
109 #
110 sequencers.append(cpu_seq)
111 l1_cntrl_nodes.append(l1_cntrl)
112 dir_cntrl_nodes.append(dir_cntrl)
113 dma_cntrl_nodes.append(dma_cntrl)
114
115 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
116
117 return (sequencers, dir_cntrl_nodes, all_cntrls)