1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 104 unchanged lines hidden (view full) ---

113 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
114
115 # Add controllers and sequencers to the appropriate lists
116 cpu_sequencers.append(cpu_seq)
117 l1_cntrl_nodes.append(l1_cntrl)
118
119 # Connect the L1 controller and the network
120 # Connect the buffers from the controller to network
121 l1_cntrl.requestFromCache = ruby_system.network.slave
122 l1_cntrl.responseFromCache = ruby_system.network.slave
123 l1_cntrl.unblockFromCache = ruby_system.network.slave
124
125 # Connect the buffers from the network to the controller
126 l1_cntrl.forwardToCache = ruby_system.network.master
127 l1_cntrl.responseToCache = ruby_system.network.master
128
129
130 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
131 assert(phys_mem_size % options.num_dirs == 0)
132 mem_module_size = phys_mem_size / options.num_dirs
133
134 #
135 # determine size and index bits for probe filter

--- 43 unchanged lines hidden (view full) ---

179
180 if options.recycle_latency:
181 dir_cntrl.recycle_latency = options.recycle_latency
182
183 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
184 dir_cntrl_nodes.append(dir_cntrl)
185
186 # Connect the directory controller to the network
187 dir_cntrl.forwardFromDir = ruby_system.network.slave
188 dir_cntrl.responseFromDir = ruby_system.network.slave
189 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
190
191 dir_cntrl.unblockToDir = ruby_system.network.master
192 dir_cntrl.responseToDir = ruby_system.network.master
193 dir_cntrl.requestToDir = ruby_system.network.master
194 dir_cntrl.dmaRequestToDir = ruby_system.network.master
195
196
197 for i, dma_port in enumerate(dma_ports):
198 #
199 # Create the Ruby objects associated with the dma controller
200 #
201 dma_seq = DMASequencer(version = i,
202 ruby_system = ruby_system,
203 slave = dma_port)
204

--- 4 unchanged lines hidden (view full) ---

209
210 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
211 dma_cntrl_nodes.append(dma_cntrl)
212
213 if options.recycle_latency:
214 dma_cntrl.recycle_latency = options.recycle_latency
215
216 # Connect the dma controller to the network
217 dma_cntrl.responseFromDir = ruby_system.network.master
218 dma_cntrl.requestToDir = ruby_system.network.slave
219
220 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
221
222 # Create the io controller and the sequencer
223 if full_system:
224 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
225 ruby_system._io_port = io_seq
226 io_controller = DMA_Controller(version = len(dma_ports),
227 dma_sequencer = io_seq,
228 ruby_system = ruby_system)
229 ruby_system.io_controller = io_controller
230
231 # Connect the dma controller to the network
232 io_controller.responseFromDir = ruby_system.network.master
233 io_controller.requestToDir = ruby_system.network.slave
234
235 all_cntrls = all_cntrls + [io_controller]
236
237 topology = create_topology(all_cntrls, options)
238 return (cpu_sequencers, dir_cntrl_nodes, topology)