1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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165 # Run each of the ruby memory controllers at a ratio of the frequency of
166 # the ruby system
167 # clk_divider value is a fix to pass regression.
168 ruby_system.memctrl_clk_domain = DerivedClockDomain(
169 clk_domain=ruby_system.clk_domain,
170 clk_divider=3)
171
172 for i in xrange(options.num_dirs):
173 dir_size = MemorySize('0B')
174 dir_size.value = mem_module_size
175
176 pf = ProbeFilter(size = pf_size, assoc = 4,
177 start_index_bit = pf_start_bit)
178
179 dir_cntrl = Directory_Controller(version = i,
180 directory = RubyDirectoryMemory(
181 version = i, size = dir_size),
182 probeFilter = pf,
183 probe_filter_enabled = options.pf_on,
184 full_bit_dir_enabled = options.dir_on,
185 transitions_per_cycle = options.ports,
186 ruby_system = ruby_system)
187
188 if options.recycle_latency:
189 dir_cntrl.recycle_latency = options.recycle_latency
190

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