MOESI_CMP_token.py (9793:6e6cefc1db1f) MOESI_CMP_token.py (9798:52679402e09c)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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153
154 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
155 l2_cntrl_nodes.append(l2_cntrl)
156
157 cntrl_count += 1
158
159 phys_mem_size = sum(map(lambda mem: mem.range.size(),
160 system.memories.unproxy(system)))
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 144 unchanged lines hidden (view full) ---

153
154 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
155 l2_cntrl_nodes.append(l2_cntrl)
156
157 cntrl_count += 1
158
159 phys_mem_size = sum(map(lambda mem: mem.range.size(),
160 system.memories.unproxy(system)))
161 assert(phys_mem_size % options.num_dirs == 0)
161 mem_module_size = phys_mem_size / options.num_dirs
162
163 # Run each of the ruby memory controllers at a ratio of the frequency of
164 # the ruby system
165 # clk_divider value is a fix to pass regression.
166 ruby_system.memctrl_clk_domain = DerivedClockDomain(
167 clk_domain=ruby_system.clk_domain,
168 clk_divider=3)

--- 54 unchanged lines hidden --- 		162 mem_module_size = phys_mem_size / options.num_dirs
163
164 # Run each of the ruby memory controllers at a ratio of the frequency of
165 # the ruby system
166 # clk_divider value is a fix to pass regression.
167 ruby_system.memctrl_clk_domain = DerivedClockDomain(
168 clk_domain=ruby_system.clk_domain,
169 clk_divider=3)

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