MOESI_CMP_token.py (9232:3bb99fab80d4) MOESI_CMP_token.py (9468:721718c62859)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 112 unchanged lines hidden (view full) ---

121 dcache = l1d_cache,
122 ruby_system = ruby_system)
123
124 l1_cntrl.sequencer = cpu_seq
125
126 if piobus != None:
127 cpu_seq.pio_port = piobus.slave
128
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 112 unchanged lines hidden (view full) ---

121 dcache = l1d_cache,
122 ruby_system = ruby_system)
123
124 l1_cntrl.sequencer = cpu_seq
125
126 if piobus != None:
127 cpu_seq.pio_port = piobus.slave
128
129 exec("system.l1_cntrl%d = l1_cntrl" % i)
129 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
130 #
131 # Add controllers and sequencers to the appropriate lists
132 #
133 cpu_sequencers.append(cpu_seq)
134 l1_cntrl_nodes.append(l1_cntrl)
135
136 cntrl_count += 1
137

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146 start_index_bit = l2_index_start)
147
148 l2_cntrl = L2Cache_Controller(version = i,
149 cntrl_id = cntrl_count,
150 L2cacheMemory = l2_cache,
151 N_tokens = n_tokens,
152 ruby_system = ruby_system)
153
130 #
131 # Add controllers and sequencers to the appropriate lists
132 #
133 cpu_sequencers.append(cpu_seq)
134 l1_cntrl_nodes.append(l1_cntrl)
135
136 cntrl_count += 1
137

--- 8 unchanged lines hidden (view full) ---

146 start_index_bit = l2_index_start)
147
148 l2_cntrl = L2Cache_Controller(version = i,
149 cntrl_id = cntrl_count,
150 L2cacheMemory = l2_cache,
151 N_tokens = n_tokens,
152 ruby_system = ruby_system)
153
154 exec("system.l2_cntrl%d = l2_cntrl" % i)
154 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
155 l2_cntrl_nodes.append(l2_cntrl)
156
157 cntrl_count += 1
158
159 phys_mem_size = sum(map(lambda mem: mem.range.size(),
160 system.memories.unproxy(system)))
161 mem_module_size = phys_mem_size / options.num_dirs
162

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175 cntrl_id = cntrl_count,
176 directory = \
177 RubyDirectoryMemory(version = i,
178 size = dir_size),
179 memBuffer = mem_cntrl,
180 l2_select_num_bits = l2_bits,
181 ruby_system = ruby_system)
182
155 l2_cntrl_nodes.append(l2_cntrl)
156
157 cntrl_count += 1
158
159 phys_mem_size = sum(map(lambda mem: mem.range.size(),
160 system.memories.unproxy(system)))
161 mem_module_size = phys_mem_size / options.num_dirs
162

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175 cntrl_id = cntrl_count,
176 directory = \
177 RubyDirectoryMemory(version = i,
178 size = dir_size),
179 memBuffer = mem_cntrl,
180 l2_select_num_bits = l2_bits,
181 ruby_system = ruby_system)
182
183 exec("system.dir_cntrl%d = dir_cntrl" % i)
183 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
184 dir_cntrl_nodes.append(dir_cntrl)
185
186 cntrl_count += 1
187
188 for i, dma_port in enumerate(dma_ports):
189 #
190 # Create the Ruby objects associated with the dma controller
191 #
192 dma_seq = DMASequencer(version = i,
193 ruby_system = ruby_system)
194
195 dma_cntrl = DMA_Controller(version = i,
196 cntrl_id = cntrl_count,
197 dma_sequencer = dma_seq,
198 ruby_system = ruby_system)
199
184 dir_cntrl_nodes.append(dir_cntrl)
185
186 cntrl_count += 1
187
188 for i, dma_port in enumerate(dma_ports):
189 #
190 # Create the Ruby objects associated with the dma controller
191 #
192 dma_seq = DMASequencer(version = i,
193 ruby_system = ruby_system)
194
195 dma_cntrl = DMA_Controller(version = i,
196 cntrl_id = cntrl_count,
197 dma_sequencer = dma_seq,
198 ruby_system = ruby_system)
199
200 exec("system.dma_cntrl%d = dma_cntrl" % i)
201 exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
200 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
201 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
202 dma_cntrl_nodes.append(dma_cntrl)
203 cntrl_count += 1
204
205 all_cntrls = l1_cntrl_nodes + \
206 l2_cntrl_nodes + \
207 dir_cntrl_nodes + \
208 dma_cntrl_nodes
209
210 topology = create_topology(all_cntrls, options)
211
212 return (cpu_sequencers, dir_cntrl_nodes, topology)
202 dma_cntrl_nodes.append(dma_cntrl)
203 cntrl_count += 1
204
205 all_cntrls = l1_cntrl_nodes + \
206 l2_cntrl_nodes + \
207 dir_cntrl_nodes + \
208 dma_cntrl_nodes
209
210 topology = create_topology(all_cntrls, options)
211
212 return (cpu_sequencers, dir_cntrl_nodes, topology)