MOESI_CMP_token.py (8180:d8587c913ccf) MOESI_CMP_token.py (8257:7226aebb77b4)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 70 unchanged lines hidden (view full) ---

79
80 #
81 # Must create the individual controllers before the network to ensure the
82 # controller constructors are called before the network constructor
83 #
84 l2_bits = int(math.log(options.num_l2caches, 2))
85 block_size_bits = int(math.log(options.cacheline_size, 2))
86
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 70 unchanged lines hidden (view full) ---

79
80 #
81 # Must create the individual controllers before the network to ensure the
82 # controller constructors are called before the network constructor
83 #
84 l2_bits = int(math.log(options.num_l2caches, 2))
85 block_size_bits = int(math.log(options.cacheline_size, 2))
86
87 cntrl_count = 0
88
87 for i in xrange(options.num_cpus):
88 #
89 # First create the Ruby objects associated with this cpu
90 #
91 l1i_cache = L1Cache(size = options.l1i_size,
92 assoc = options.l1i_assoc,
93 start_index_bit = block_size_bits)
94 l1d_cache = L1Cache(size = options.l1d_size,

--- 5 unchanged lines hidden (view full) ---

100 dcache = l1d_cache,
101 physMemPort = system.physmem.port,
102 physmem = system.physmem)
103
104 if piobus != None:
105 cpu_seq.pio_port = piobus.port
106
107 l1_cntrl = L1Cache_Controller(version = i,
89 for i in xrange(options.num_cpus):
90 #
91 # First create the Ruby objects associated with this cpu
92 #
93 l1i_cache = L1Cache(size = options.l1i_size,
94 assoc = options.l1i_assoc,
95 start_index_bit = block_size_bits)
96 l1d_cache = L1Cache(size = options.l1d_size,

--- 5 unchanged lines hidden (view full) ---

102 dcache = l1d_cache,
103 physMemPort = system.physmem.port,
104 physmem = system.physmem)
105
106 if piobus != None:
107 cpu_seq.pio_port = piobus.port
108
109 l1_cntrl = L1Cache_Controller(version = i,
110 cntrl_id = cntrl_count,
108 sequencer = cpu_seq,
109 L1IcacheMemory = l1i_cache,
110 L1DcacheMemory = l1d_cache,
111 l2_select_num_bits = l2_bits,
112 N_tokens = n_tokens,
113 retry_threshold = \
114 options.l1_retries,
115 fixed_timeout_latency = \

--- 5 unchanged lines hidden (view full) ---

121
122 exec("system.l1_cntrl%d = l1_cntrl" % i)
123 #
124 # Add controllers and sequencers to the appropriate lists
125 #
126 cpu_sequencers.append(cpu_seq)
127 l1_cntrl_nodes.append(l1_cntrl)
128
111 sequencer = cpu_seq,
112 L1IcacheMemory = l1i_cache,
113 L1DcacheMemory = l1d_cache,
114 l2_select_num_bits = l2_bits,
115 N_tokens = n_tokens,
116 retry_threshold = \
117 options.l1_retries,
118 fixed_timeout_latency = \

--- 5 unchanged lines hidden (view full) ---

124
125 exec("system.l1_cntrl%d = l1_cntrl" % i)
126 #
127 # Add controllers and sequencers to the appropriate lists
128 #
129 cpu_sequencers.append(cpu_seq)
130 l1_cntrl_nodes.append(l1_cntrl)
131
132 cntrl_count += 1
133
129 l2_index_start = block_size_bits + l2_bits
130
131 for i in xrange(options.num_l2caches):
132 #
133 # First create the Ruby objects associated with this cpu
134 #
135 l2_cache = L2Cache(size = options.l2_size,
136 assoc = options.l2_assoc,
137 start_index_bit = l2_index_start)
138
139 l2_cntrl = L2Cache_Controller(version = i,
134 l2_index_start = block_size_bits + l2_bits
135
136 for i in xrange(options.num_l2caches):
137 #
138 # First create the Ruby objects associated with this cpu
139 #
140 l2_cache = L2Cache(size = options.l2_size,
141 assoc = options.l2_assoc,
142 start_index_bit = l2_index_start)
143
144 l2_cntrl = L2Cache_Controller(version = i,
145 cntrl_id = cntrl_count,
140 L2cacheMemory = l2_cache,
141 N_tokens = n_tokens)
142
143 exec("system.l2_cntrl%d = l2_cntrl" % i)
144 l2_cntrl_nodes.append(l2_cntrl)
146 L2cacheMemory = l2_cache,
147 N_tokens = n_tokens)
148
149 exec("system.l2_cntrl%d = l2_cntrl" % i)
150 l2_cntrl_nodes.append(l2_cntrl)
151
152 cntrl_count += 1
145
146 phys_mem_size = long(system.physmem.range.second) - \
147 long(system.physmem.range.first) + 1
148 mem_module_size = phys_mem_size / options.num_dirs
149
150 for i in xrange(options.num_dirs):
151 #
152 # Create the Ruby objects associated with the directory controller
153 #
154
155 mem_cntrl = RubyMemoryControl(version = i)
156
157 dir_size = MemorySize('0B')
158 dir_size.value = mem_module_size
159
160 dir_cntrl = Directory_Controller(version = i,
153
154 phys_mem_size = long(system.physmem.range.second) - \
155 long(system.physmem.range.first) + 1
156 mem_module_size = phys_mem_size / options.num_dirs
157
158 for i in xrange(options.num_dirs):
159 #
160 # Create the Ruby objects associated with the directory controller
161 #
162
163 mem_cntrl = RubyMemoryControl(version = i)
164
165 dir_size = MemorySize('0B')
166 dir_size.value = mem_module_size
167
168 dir_cntrl = Directory_Controller(version = i,
169 cntrl_id = cntrl_count,
161 directory = \
162 RubyDirectoryMemory(version = i,
163 size = \
164 dir_size),
165 memBuffer = mem_cntrl,
166 l2_select_num_bits = l2_bits)
167
168 exec("system.dir_cntrl%d = dir_cntrl" % i)
169 dir_cntrl_nodes.append(dir_cntrl)
170
170 directory = \
171 RubyDirectoryMemory(version = i,
172 size = \
173 dir_size),
174 memBuffer = mem_cntrl,
175 l2_select_num_bits = l2_bits)
176
177 exec("system.dir_cntrl%d = dir_cntrl" % i)
178 dir_cntrl_nodes.append(dir_cntrl)
179
180 cntrl_count += 1
181
171 for i, dma_device in enumerate(dma_devices):
172 #
173 # Create the Ruby objects associated with the dma controller
174 #
175 dma_seq = DMASequencer(version = i,
176 physMemPort = system.physmem.port,
177 physmem = system.physmem)
178
179 dma_cntrl = DMA_Controller(version = i,
182 for i, dma_device in enumerate(dma_devices):
183 #
184 # Create the Ruby objects associated with the dma controller
185 #
186 dma_seq = DMASequencer(version = i,
187 physMemPort = system.physmem.port,
188 physmem = system.physmem)
189
190 dma_cntrl = DMA_Controller(version = i,
191 cntrl_id = cntrl_count,
180 dma_sequencer = dma_seq)
181
182 exec("system.dma_cntrl%d = dma_cntrl" % i)
183 if dma_device.type == 'MemTest':
184 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
185 else:
186 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
187 dma_cntrl_nodes.append(dma_cntrl)
188
192 dma_sequencer = dma_seq)
193
194 exec("system.dma_cntrl%d = dma_cntrl" % i)
195 if dma_device.type == 'MemTest':
196 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
197 else:
198 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
199 dma_cntrl_nodes.append(dma_cntrl)
200
201 cntrl_count += 1
202
189 all_cntrls = l1_cntrl_nodes + \
190 l2_cntrl_nodes + \
191 dir_cntrl_nodes + \
192 dma_cntrl_nodes
193
194 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
203 all_cntrls = l1_cntrl_nodes + \
204 l2_cntrl_nodes + \
205 dir_cntrl_nodes + \
206 dma_cntrl_nodes
207
208 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)