MOESI_CMP_token.py (7561:02a9a597fce4) MOESI_CMP_token.py (7564:3559d47839a1)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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76 l2_cntrl_nodes = []
77 dir_cntrl_nodes = []
78 dma_cntrl_nodes = []
79
80 #
81 # Must create the individual controllers before the network to ensure the
82 # controller constructors are called before the network constructor
83 #
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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76 l2_cntrl_nodes = []
77 dir_cntrl_nodes = []
78 dma_cntrl_nodes = []
79
80 #
81 # Must create the individual controllers before the network to ensure the
82 # controller constructors are called before the network constructor
83 #
84 l2_bits = int(math.log(options.num_l2caches, 2))
84
85 for i in xrange(options.num_cpus):
86 #
87 # First create the Ruby objects associated with this cpu
88 #
89 l1i_cache = L1Cache(size = options.l1i_size,
90 assoc = options.l1i_assoc)
91 l1d_cache = L1Cache(size = options.l1d_size,

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99
100 if piobus != None:
101 cpu_seq.pio_port = piobus.port
102
103 l1_cntrl = L1Cache_Controller(version = i,
104 sequencer = cpu_seq,
105 L1IcacheMemory = l1i_cache,
106 L1DcacheMemory = l1d_cache,
85
86 for i in xrange(options.num_cpus):
87 #
88 # First create the Ruby objects associated with this cpu
89 #
90 l1i_cache = L1Cache(size = options.l1i_size,
91 assoc = options.l1i_assoc)
92 l1d_cache = L1Cache(size = options.l1d_size,

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100
101 if piobus != None:
102 cpu_seq.pio_port = piobus.port
103
104 l1_cntrl = L1Cache_Controller(version = i,
105 sequencer = cpu_seq,
106 L1IcacheMemory = l1i_cache,
107 L1DcacheMemory = l1d_cache,
107 l2_select_num_bits = \
108 math.log(options.num_l2caches,
109 2),
108 l2_select_num_bits = l2_bits,
110 N_tokens = n_tokens,
111 retry_threshold = \
112 options.l1_retries,
113 fixed_timeout_latency = \
114 options.timeout_latency,
115 dynamic_timeout_enabled = \
116 not options.disable_dyn_timeouts,
117 no_mig_atomic = not \

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124 cpu_sequencers.append(cpu_seq)
125 l1_cntrl_nodes.append(l1_cntrl)
126
127 for i in xrange(options.num_l2caches):
128 #
129 # First create the Ruby objects associated with this cpu
130 #
131 l2_cache = L2Cache(size = options.l2_size,
109 N_tokens = n_tokens,
110 retry_threshold = \
111 options.l1_retries,
112 fixed_timeout_latency = \
113 options.timeout_latency,
114 dynamic_timeout_enabled = \
115 not options.disable_dyn_timeouts,
116 no_mig_atomic = not \

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123 cpu_sequencers.append(cpu_seq)
124 l1_cntrl_nodes.append(l1_cntrl)
125
126 for i in xrange(options.num_l2caches):
127 #
128 # First create the Ruby objects associated with this cpu
129 #
130 l2_cache = L2Cache(size = options.l2_size,
132 assoc = options.l2_assoc)
131 assoc = options.l2_assoc,
132 start_index_bit = l2_bits)
133
134 l2_cntrl = L2Cache_Controller(version = i,
135 L2cacheMemory = l2_cache,
136 N_tokens = n_tokens)
137
138 exec("system.l2_cntrl%d = l2_cntrl" % i)
139 l2_cntrl_nodes.append(l2_cntrl)
140

--- 52 unchanged lines hidden --- 		133
134 l2_cntrl = L2Cache_Controller(version = i,
135 L2cacheMemory = l2_cache,
136 N_tokens = n_tokens)
137
138 exec("system.l2_cntrl%d = l2_cntrl" % i)
139 l2_cntrl_nodes.append(l2_cntrl)
140

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