MOESI_CMP_token.py (6908:0e1d7624e641) MOESI_CMP_token.py (7015:6c91d41dfc12)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 68 unchanged lines hidden (view full) ---

77 #
78 # First create the Ruby objects associated with this cpu
79 #
80 l1i_cache = L1Cache(size = options.l1i_size,
81 assoc = options.l1i_assoc)
82 l1d_cache = L1Cache(size = options.l1d_size,
83 assoc = options.l1d_assoc)
84
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 68 unchanged lines hidden (view full) ---

77 #
78 # First create the Ruby objects associated with this cpu
79 #
80 l1i_cache = L1Cache(size = options.l1i_size,
81 assoc = options.l1i_assoc)
82 l1d_cache = L1Cache(size = options.l1d_size,
83 assoc = options.l1d_assoc)
84
85 cpu_seq = RubySequencer(icache = l1i_cache,
85 cpu_seq = RubySequencer(version = i,
86 icache = l1i_cache,
86 dcache = l1d_cache,
87 physMemPort = phys_mem.port,
88 physmem = phys_mem)
89
90 if piobus != None:
91 cpu_seq.pio_port = piobus.port
92
93 l1_cntrl = L1Cache_Controller(version = i,

--- 68 unchanged lines hidden --- 		87 dcache = l1d_cache,
88 physMemPort = phys_mem.port,
89 physmem = phys_mem)
90
91 if piobus != None:
92 cpu_seq.pio_port = piobus.port
93
94 l1_cntrl = L1Cache_Controller(version = i,

--- 68 unchanged lines hidden ---