MOESI_CMP_token.py (12598:b80b2d9a251b) MOESI_CMP_token.py (12976:125099a94768)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 178 unchanged lines hidden (view full) ---

187 # Run each of the ruby memory controllers at a ratio of the frequency of
188 # the ruby system
189 # clk_divider value is a fix to pass regression.
190 ruby_system.memctrl_clk_domain = DerivedClockDomain(
191 clk_domain=ruby_system.clk_domain,
192 clk_divider=3)
193
194 mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 178 unchanged lines hidden (view full) ---

187 # Run each of the ruby memory controllers at a ratio of the frequency of
188 # the ruby system
189 # clk_divider value is a fix to pass regression.
190 ruby_system.memctrl_clk_domain = DerivedClockDomain(
191 clk_domain=ruby_system.clk_domain,
192 clk_divider=3)
193
194 mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
195 options, system.mem_ranges, bootmem, ruby_system, system)
195 options, bootmem, ruby_system, system)
196 dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
197 if rom_dir_cntrl_node is not None:
198 dir_cntrl_nodes.append(rom_dir_cntrl_node)
199 for dir_cntrl in dir_cntrl_nodes:
200 dir_cntrl.l2_select_num_bits = l2_bits
201 # Connect the directory controllers and the network
202 dir_cntrl.requestToDir = MessageBuffer()
203 dir_cntrl.requestToDir.slave = ruby_system.network.master

--- 68 unchanged lines hidden --- 		196 dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
197 if rom_dir_cntrl_node is not None:
198 dir_cntrl_nodes.append(rom_dir_cntrl_node)
199 for dir_cntrl in dir_cntrl_nodes:
200 dir_cntrl.l2_select_num_bits = l2_bits
201 # Connect the directory controllers and the network
202 dir_cntrl.requestToDir = MessageBuffer()
203 dir_cntrl.requestToDir.slave = ruby_system.network.master

--- 68 unchanged lines hidden ---