MOESI_CMP_token.py (11065:37e19af67f62) MOESI_CMP_token.py (11266:452e10b868ea)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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86 #
87 l1i_cache = L1Cache(size = options.l1i_size,
88 assoc = options.l1i_assoc,
89 start_index_bit = block_size_bits)
90 l1d_cache = L1Cache(size = options.l1d_size,
91 assoc = options.l1d_assoc,
92 start_index_bit = block_size_bits)
93
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 77 unchanged lines hidden (view full) ---

86 #
87 l1i_cache = L1Cache(size = options.l1i_size,
88 assoc = options.l1i_assoc,
89 start_index_bit = block_size_bits)
90 l1d_cache = L1Cache(size = options.l1d_size,
91 assoc = options.l1d_assoc,
92 start_index_bit = block_size_bits)
93
94 l1_cntrl = L1Cache_Controller(version = i,
95 L1Icache = l1i_cache,
96 L1Dcache = l1d_cache,
97 l2_select_num_bits = l2_bits,
98 N_tokens = n_tokens,
99 retry_threshold = \
100 options.l1_retries,
101 fixed_timeout_latency = \
102 options.timeout_latency,
103 dynamic_timeout_enabled = \
104 not options.disable_dyn_timeouts,
105 no_mig_atomic = not \
106 options.allow_atomic_migration,
107 send_evictions = send_evicts(options),
108 transitions_per_cycle = options.ports,
109 clk_domain=system.cpu[i].clk_domain,
110 ruby_system = ruby_system)
94 # the ruby random tester reuses num_cpus to specify the
95 # number of cpu ports connected to the tester object, which
96 # is stored in system.cpu. because there is only ever one
97 # tester object, num_cpus is not necessarily equal to the
98 # size of system.cpu; therefore if len(system.cpu) == 1
99 # we use system.cpu[0] to set the clk_domain, thereby ensuring
100 # we don't index off the end of the cpu list.
101 if len(system.cpu) == 1:
102 clk_domain = system.cpu[0].clk_domain
103 else:
104 clk_domain = system.cpu[i].clk_domain
111
105
112 cpu_seq = RubySequencer(version = i,
113 icache = l1i_cache,
114 dcache = l1d_cache,
115 clk_domain=system.cpu[i].clk_domain,
116 ruby_system = ruby_system)
106 l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
107 L1Dcache=l1d_cache,
108 l2_select_num_bits=l2_bits,
109 N_tokens=n_tokens,
110 retry_threshold=options.l1_retries,
111 fixed_timeout_latency=\
112 options.timeout_latency,
113 dynamic_timeout_enabled=\
114 not options.disable_dyn_timeouts,
115 no_mig_atomic=not \
116 options.allow_atomic_migration,
117 send_evictions=send_evicts(options),
118 transitions_per_cycle=options.ports,
119 clk_domain=clk_domain,
120 ruby_system=ruby_system)
117
121
122 cpu_seq = RubySequencer(version=i, icache=l1i_cache,
123 dcache=l1d_cache, clk_domain=clk_domain,
124 ruby_system=ruby_system)
125
118 l1_cntrl.sequencer = cpu_seq
119 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
120
121 # Add controllers and sequencers to the appropriate lists
122 cpu_sequencers.append(cpu_seq)
123 l1_cntrl_nodes.append(l1_cntrl)
124
125 # Connect the L1 controllers and the network

--- 149 unchanged lines hidden --- 		126 l1_cntrl.sequencer = cpu_seq
127 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
128
129 # Add controllers and sequencers to the appropriate lists
130 cpu_sequencers.append(cpu_seq)
131 l1_cntrl_nodes.append(l1_cntrl)
132
133 # Connect the L1 controllers and the network

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