MOESI_CMP_token.py (10300:ed3816dae6d5) MOESI_CMP_token.py (10311:ad9c042dce54)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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119 icache = l1i_cache,
120 dcache = l1d_cache,
121 clk_domain=system.cpu[i].clk_domain,
122 ruby_system = ruby_system)
123
124 l1_cntrl.sequencer = cpu_seq
125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
126
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 110 unchanged lines hidden (view full) ---

119 icache = l1i_cache,
120 dcache = l1d_cache,
121 clk_domain=system.cpu[i].clk_domain,
122 ruby_system = ruby_system)
123
124 l1_cntrl.sequencer = cpu_seq
125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
126
127 #
128 # Add controllers and sequencers to the appropriate lists
127 # Add controllers and sequencers to the appropriate lists
129 #
130 cpu_sequencers.append(cpu_seq)
131 l1_cntrl_nodes.append(l1_cntrl)
132
128 cpu_sequencers.append(cpu_seq)
129 l1_cntrl_nodes.append(l1_cntrl)
130
131 # Connect the L1 controllers and the network
132 l1_cntrl.requestFromL1Cache = ruby_system.network.slave
133 l1_cntrl.responseFromL1Cache = ruby_system.network.slave
134 l1_cntrl.persistentFromL1Cache = ruby_system.network.slave
135
136 l1_cntrl.requestToL1Cache = ruby_system.network.master
137 l1_cntrl.responseToL1Cache = ruby_system.network.master
138 l1_cntrl.persistentToL1Cache = ruby_system.network.master
139
140
133 l2_index_start = block_size_bits + l2_bits
134
135 for i in xrange(options.num_l2caches):
136 #
137 # First create the Ruby objects associated with this cpu
138 #
139 l2_cache = L2Cache(size = options.l2_size,
140 assoc = options.l2_assoc,
141 start_index_bit = l2_index_start)
142
143 l2_cntrl = L2Cache_Controller(version = i,
144 L2cache = l2_cache,
145 N_tokens = n_tokens,
146 transitions_per_cycle = options.ports,
147 ruby_system = ruby_system)
148
149 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
150 l2_cntrl_nodes.append(l2_cntrl)
151
141 l2_index_start = block_size_bits + l2_bits
142
143 for i in xrange(options.num_l2caches):
144 #
145 # First create the Ruby objects associated with this cpu
146 #
147 l2_cache = L2Cache(size = options.l2_size,
148 assoc = options.l2_assoc,
149 start_index_bit = l2_index_start)
150
151 l2_cntrl = L2Cache_Controller(version = i,
152 L2cache = l2_cache,
153 N_tokens = n_tokens,
154 transitions_per_cycle = options.ports,
155 ruby_system = ruby_system)
156
157 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
158 l2_cntrl_nodes.append(l2_cntrl)
159
160 # Connect the L2 controllers and the network
161 l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
162 l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
163 l2_cntrl.responseFromL2Cache = ruby_system.network.slave
164
165 l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
166 l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
167 l2_cntrl.responseToL2Cache = ruby_system.network.master
168 l2_cntrl.persistentToL2Cache = ruby_system.network.master
169
170
152 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
153 assert(phys_mem_size % options.num_dirs == 0)
154 mem_module_size = phys_mem_size / options.num_dirs
155
156 # Run each of the ruby memory controllers at a ratio of the frequency of
157 # the ruby system
158 # clk_divider value is a fix to pass regression.
159 ruby_system.memctrl_clk_domain = DerivedClockDomain(

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181 memBuffer = mem_cntrl,
182 l2_select_num_bits = l2_bits,
183 transitions_per_cycle = options.ports,
184 ruby_system = ruby_system)
185
186 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
187 dir_cntrl_nodes.append(dir_cntrl)
188
171 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
172 assert(phys_mem_size % options.num_dirs == 0)
173 mem_module_size = phys_mem_size / options.num_dirs
174
175 # Run each of the ruby memory controllers at a ratio of the frequency of
176 # the ruby system
177 # clk_divider value is a fix to pass regression.
178 ruby_system.memctrl_clk_domain = DerivedClockDomain(

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200 memBuffer = mem_cntrl,
201 l2_select_num_bits = l2_bits,
202 transitions_per_cycle = options.ports,
203 ruby_system = ruby_system)
204
205 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
206 dir_cntrl_nodes.append(dir_cntrl)
207
208 # Connect the directory controllers and the network
209 dir_cntrl.requestToDir = ruby_system.network.master
210 dir_cntrl.responseToDir = ruby_system.network.master
211 dir_cntrl.persistentToDir = ruby_system.network.master
212 dir_cntrl.dmaRequestToDir = ruby_system.network.master
213
214 dir_cntrl.requestFromDir = ruby_system.network.slave
215 dir_cntrl.responseFromDir = ruby_system.network.slave
216 dir_cntrl.persistentFromDir = ruby_system.network.slave
217 dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
218
219
189 for i, dma_port in enumerate(dma_ports):
190 #
191 # Create the Ruby objects associated with the dma controller
192 #
193 dma_seq = DMASequencer(version = i,
194 ruby_system = ruby_system)
195
196 dma_cntrl = DMA_Controller(version = i,

--- 16 unchanged lines hidden --- 		220 for i, dma_port in enumerate(dma_ports):
221 #
222 # Create the Ruby objects associated with the dma controller
223 #
224 dma_seq = DMASequencer(version = i,
225 ruby_system = ruby_system)
226
227 dma_cntrl = DMA_Controller(version = i,

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