1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 latency = 2 41 42# 43# Note: the L2 Cache latency is not currently used 44# 45class L2Cache(RubyCache): 46 latency = 10 47 48def define_options(parser): 49 parser.add_option("--l1-retries", type="int", default=1, 50 help="Token_CMP: # of l1 retries before going persistent") 51 parser.add_option("--timeout-latency", type="int", default=300, 52 help="Token_CMP: cycles until issuing again"); 53 parser.add_option("--disable-dyn-timeouts", action="store_true", 54 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 55 parser.add_option("--allow-atomic-migration", action="store_true", 56 help="allow migratory sharing for atomic only accessed blocks") 57 58def create_system(options, system, dma_ports, ruby_system): 59 60 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 61 panic("This script requires the MOESI_CMP_token protocol to be built.") 62 63 # 64 # number of tokens that the owner passes to requests so that shared blocks can 65 # respond to read requests 66 # 67 n_tokens = options.num_cpus + 1 68 69 cpu_sequencers = [] 70 71 # 72 # The ruby network creation expects the list of nodes in the system to be 73 # consistent with the NetDest list. Therefore the l1 controller nodes must be 74 # listed before the directory nodes and directory nodes before dma nodes, etc. 75 # 76 l1_cntrl_nodes = [] 77 l2_cntrl_nodes = [] 78 dir_cntrl_nodes = [] 79 dma_cntrl_nodes = [] 80 81 # 82 # Must create the individual controllers before the network to ensure the 83 # controller constructors are called before the network constructor 84 # 85 l2_bits = int(math.log(options.num_l2caches, 2)) 86 block_size_bits = int(math.log(options.cacheline_size, 2)) 87 88 for i in xrange(options.num_cpus): 89 # 90 # First create the Ruby objects associated with this cpu 91 # 92 l1i_cache = L1Cache(size = options.l1i_size, 93 assoc = options.l1i_assoc, 94 start_index_bit = block_size_bits) 95 l1d_cache = L1Cache(size = options.l1d_size, 96 assoc = options.l1d_assoc, 97 start_index_bit = block_size_bits) 98 99 l1_cntrl = L1Cache_Controller(version = i, 100 L1Icache = l1i_cache, 101 L1Dcache = l1d_cache, 102 l2_select_num_bits = l2_bits, 103 N_tokens = n_tokens, 104 retry_threshold = \ 105 options.l1_retries, 106 fixed_timeout_latency = \ 107 options.timeout_latency, 108 dynamic_timeout_enabled = \ 109 not options.disable_dyn_timeouts, 110 no_mig_atomic = not \ 111 options.allow_atomic_migration, 112 send_evictions = ( 113 options.cpu_type == "detailed"), 114 transitions_per_cycle = options.ports,
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122 ruby_system = ruby_system) 123 124 l1_cntrl.sequencer = cpu_seq 125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 126 127 # 128 # Add controllers and sequencers to the appropriate lists 129 # 130 cpu_sequencers.append(cpu_seq) 131 l1_cntrl_nodes.append(l1_cntrl) 132 133 l2_index_start = block_size_bits + l2_bits 134 135 for i in xrange(options.num_l2caches): 136 # 137 # First create the Ruby objects associated with this cpu 138 # 139 l2_cache = L2Cache(size = options.l2_size, 140 assoc = options.l2_assoc, 141 start_index_bit = l2_index_start) 142 143 l2_cntrl = L2Cache_Controller(version = i, 144 L2cache = l2_cache, 145 N_tokens = n_tokens, 146 transitions_per_cycle = options.ports, 147 ruby_system = ruby_system) 148 149 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 150 l2_cntrl_nodes.append(l2_cntrl) 151 152 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 153 assert(phys_mem_size % options.num_dirs == 0) 154 mem_module_size = phys_mem_size / options.num_dirs 155 156 # Run each of the ruby memory controllers at a ratio of the frequency of 157 # the ruby system 158 # clk_divider value is a fix to pass regression. 159 ruby_system.memctrl_clk_domain = DerivedClockDomain( 160 clk_domain=ruby_system.clk_domain, 161 clk_divider=3) 162 163 for i in xrange(options.num_dirs): 164 # 165 # Create the Ruby objects associated with the directory controller 166 # 167 168 mem_cntrl = RubyMemoryControl( 169 clk_domain = ruby_system.memctrl_clk_domain, 170 version = i, 171 ruby_system = ruby_system) 172 173 dir_size = MemorySize('0B') 174 dir_size.value = mem_module_size 175 176 dir_cntrl = Directory_Controller(version = i, 177 directory = \ 178 RubyDirectoryMemory(version = i, 179 use_map = options.use_map, 180 size = dir_size), 181 memBuffer = mem_cntrl, 182 l2_select_num_bits = l2_bits, 183 transitions_per_cycle = options.ports, 184 ruby_system = ruby_system) 185 186 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 187 dir_cntrl_nodes.append(dir_cntrl) 188 189 for i, dma_port in enumerate(dma_ports): 190 # 191 # Create the Ruby objects associated with the dma controller 192 # 193 dma_seq = DMASequencer(version = i, 194 ruby_system = ruby_system) 195 196 dma_cntrl = DMA_Controller(version = i, 197 dma_sequencer = dma_seq, 198 transitions_per_cycle = options.ports, 199 ruby_system = ruby_system) 200 201 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 202 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 203 dma_cntrl_nodes.append(dma_cntrl) 204 205 all_cntrls = l1_cntrl_nodes + \ 206 l2_cntrl_nodes + \ 207 dir_cntrl_nodes + \ 208 dma_cntrl_nodes 209 210 topology = create_topology(all_cntrls, options) 211 212 return (cpu_sequencers, dir_cntrl_nodes, topology)
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