1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 142 unchanged lines hidden (view full) --- 151 N_tokens = n_tokens, 152 ruby_system = ruby_system) 153 154 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 155 l2_cntrl_nodes.append(l2_cntrl) 156 157 cntrl_count += 1 158 |
159 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) |
160 assert(phys_mem_size % options.num_dirs == 0) 161 mem_module_size = phys_mem_size / options.num_dirs 162 163 # Run each of the ruby memory controllers at a ratio of the frequency of 164 # the ruby system 165 # clk_divider value is a fix to pass regression. 166 ruby_system.memctrl_clk_domain = DerivedClockDomain( 167 clk_domain=ruby_system.clk_domain, --- 55 unchanged lines hidden --- |