1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 86 unchanged lines hidden (view full) --- 95 assoc = options.l1i_assoc, 96 start_index_bit = block_size_bits) 97 l1d_cache = L1Cache(size = options.l1d_size, 98 assoc = options.l1d_assoc, 99 start_index_bit = block_size_bits) 100 101 l1_cntrl = L1Cache_Controller(version = i, 102 cntrl_id = cntrl_count, |
103 L1Icache = l1i_cache, 104 L1Dcache = l1d_cache, |
105 l2_select_num_bits = l2_bits, 106 N_tokens = n_tokens, 107 retry_threshold = \ 108 options.l1_retries, 109 fixed_timeout_latency = \ 110 options.timeout_latency, 111 dynamic_timeout_enabled = \ 112 not options.disable_dyn_timeouts, --- 29 unchanged lines hidden (view full) --- 142 # First create the Ruby objects associated with this cpu 143 # 144 l2_cache = L2Cache(size = options.l2_size, 145 assoc = options.l2_assoc, 146 start_index_bit = l2_index_start) 147 148 l2_cntrl = L2Cache_Controller(version = i, 149 cntrl_id = cntrl_count, |
150 L2cache = l2_cache, |
151 N_tokens = n_tokens, 152 ruby_system = ruby_system) 153 154 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 155 l2_cntrl_nodes.append(l2_cntrl) 156 157 cntrl_count += 1 158 --- 55 unchanged lines hidden --- |