1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv |
34from Ruby import create_topology |
35 36# 37# Note: the L1 Cache latency is only used by the sequencer on fast path hits 38# 39class L1Cache(RubyCache): 40 latency = 2 41 42# --- 159 unchanged lines hidden (view full) --- 202 dma_cntrl_nodes.append(dma_cntrl) 203 cntrl_count += 1 204 205 all_cntrls = l1_cntrl_nodes + \ 206 l2_cntrl_nodes + \ 207 dir_cntrl_nodes + \ 208 dma_cntrl_nodes 209 |
210 topology = create_topology(all_cntrls, options) 211 212 return (cpu_sequencers, dir_cntrl_nodes, topology) |