1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 175 unchanged lines hidden (view full) --- 184 cntrl_count += 1 185 186 for i, dma_device in enumerate(dma_devices): 187 # 188 # Create the Ruby objects associated with the dma controller 189 # 190 dma_seq = DMASequencer(version = i, 191 physMemPort = system.physmem.port, |
192 physmem = system.physmem, 193 ruby_system = ruby_system) |
194 195 dma_cntrl = DMA_Controller(version = i, 196 cntrl_id = cntrl_count, |
197 dma_sequencer = dma_seq, 198 ruby_system = ruby_system) |
199 200 exec("system.dma_cntrl%d = dma_cntrl" % i) 201 if dma_device.type == 'MemTest': 202 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) 203 else: 204 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) 205 dma_cntrl_nodes.append(dma_cntrl) 206 207 cntrl_count += 1 208 209 all_cntrls = l1_cntrl_nodes + \ 210 l2_cntrl_nodes + \ 211 dir_cntrl_nodes + \ 212 dma_cntrl_nodes 213 214 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |