1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 83 unchanged lines hidden (view full) --- 92 # 93 l1i_cache = L1Cache(size = options.l1i_size, 94 assoc = options.l1i_assoc, 95 start_index_bit = block_size_bits) 96 l1d_cache = L1Cache(size = options.l1d_size, 97 assoc = options.l1d_assoc, 98 start_index_bit = block_size_bits) 99 |
100 l1_cntrl = L1Cache_Controller(version = i, 101 cntrl_id = cntrl_count, |
102 L1IcacheMemory = l1i_cache, 103 L1DcacheMemory = l1d_cache, 104 l2_select_num_bits = l2_bits, 105 N_tokens = n_tokens, 106 retry_threshold = \ 107 options.l1_retries, 108 fixed_timeout_latency = \ 109 options.timeout_latency, 110 dynamic_timeout_enabled = \ 111 not options.disable_dyn_timeouts, 112 no_mig_atomic = not \ 113 options.allow_atomic_migration) 114 |
115 cpu_seq = RubySequencer(version = i, 116 icache = l1i_cache, 117 dcache = l1d_cache, 118 physMemPort = system.physmem.port, 119 physmem = system.physmem) 120 121 l1_cntrl.sequencer = cpu_seq 122 123 if piobus != None: 124 cpu_seq.pio_port = piobus.port 125 |
126 exec("system.l1_cntrl%d = l1_cntrl" % i) 127 # 128 # Add controllers and sequencers to the appropriate lists 129 # 130 cpu_sequencers.append(cpu_seq) 131 l1_cntrl_nodes.append(l1_cntrl) 132 133 cntrl_count += 1 --- 76 unchanged lines hidden --- |