1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 68 unchanged lines hidden (view full) --- 77 dir_cntrl_nodes = [] 78 dma_cntrl_nodes = [] 79 80 # 81 # Must create the individual controllers before the network to ensure the 82 # controller constructors are called before the network constructor 83 # 84 l2_bits = int(math.log(options.num_l2caches, 2)) |
85 block_size_bits = int(math.log(options.cacheline_size, 2)) |
86 87 for i in xrange(options.num_cpus): 88 # 89 # First create the Ruby objects associated with this cpu 90 # 91 l1i_cache = L1Cache(size = options.l1i_size, |
92 assoc = options.l1i_assoc, 93 start_index_bit = block_size_bits) |
94 l1d_cache = L1Cache(size = options.l1d_size, |
95 assoc = options.l1d_assoc, 96 start_index_bit = block_size_bits) |
97 98 cpu_seq = RubySequencer(version = i, 99 icache = l1i_cache, 100 dcache = l1d_cache, 101 physMemPort = system.physmem.port, 102 physmem = system.physmem) 103 104 if piobus != None: --- 16 unchanged lines hidden (view full) --- 121 122 exec("system.l1_cntrl%d = l1_cntrl" % i) 123 # 124 # Add controllers and sequencers to the appropriate lists 125 # 126 cpu_sequencers.append(cpu_seq) 127 l1_cntrl_nodes.append(l1_cntrl) 128 |
129 l2_index_start = block_size_bits + l2_bits 130 |
131 for i in xrange(options.num_l2caches): 132 # 133 # First create the Ruby objects associated with this cpu 134 # 135 l2_cache = L2Cache(size = options.l2_size, 136 assoc = options.l2_assoc, |
137 start_index_bit = l2_index_start) |
138 139 l2_cntrl = L2Cache_Controller(version = i, 140 L2cacheMemory = l2_cache, 141 N_tokens = n_tokens) 142 143 exec("system.l2_cntrl%d = l2_cntrl" % i) 144 l2_cntrl_nodes.append(l2_cntrl) 145 --- 12 unchanged lines hidden (view full) --- 158 dir_size.value = mem_module_size 159 160 dir_cntrl = Directory_Controller(version = i, 161 directory = \ 162 RubyDirectoryMemory(version = i, 163 size = \ 164 dir_size), 165 memBuffer = mem_cntrl, |
166 l2_select_num_bits = l2_bits) |
167 168 exec("system.dir_cntrl%d = dir_cntrl" % i) 169 dir_cntrl_nodes.append(dir_cntrl) 170 171 for i, dma_device in enumerate(dma_devices): 172 # 173 # Create the Ruby objects associated with the dma controller 174 # --- 20 unchanged lines hidden --- |