1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 164 unchanged lines hidden (view full) --- 173 physMemPort = system.physmem.port, 174 physmem = system.physmem) 175 176 dma_cntrl = DMA_Controller(version = i, 177 dma_sequencer = dma_seq) 178 179 exec("system.dma_cntrl%d = dma_cntrl" % i) 180 if dma_device.type == 'MemTest': |
181 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i) |
182 else: |
183 exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i) |
184 dma_cntrl_nodes.append(dma_cntrl) 185 186 all_cntrls = l1_cntrl_nodes + \ 187 l2_cntrl_nodes + \ 188 dir_cntrl_nodes + \ 189 dma_cntrl_nodes 190 191 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |