1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 38 unchanged lines hidden (view full) --- 47def define_options(parser): 48 parser.add_option("--l1-retries", type="int", default=1, 49 help="Token_CMP: # of l1 retries before going persistent") 50 parser.add_option("--timeout-latency", type="int", default=300, 51 help="Token_CMP: cycles until issuing again"); 52 parser.add_option("--disable-dyn-timeouts", action="store_true", 53 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 54 |
55def create_system(options, system, piobus, dma_devices): |
56 57 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 58 panic("This script requires the MOESI_CMP_token protocol to be built.") 59 60 # 61 # number of tokens that the owner passes to requests so that shared blocks can 62 # respond to read requests 63 # --- 23 unchanged lines hidden (view full) --- 87 l1i_cache = L1Cache(size = options.l1i_size, 88 assoc = options.l1i_assoc) 89 l1d_cache = L1Cache(size = options.l1d_size, 90 assoc = options.l1d_assoc) 91 92 cpu_seq = RubySequencer(version = i, 93 icache = l1i_cache, 94 dcache = l1d_cache, |
95 physMemPort = system.physmem.port, 96 physmem = system.physmem) |
97 98 if piobus != None: 99 cpu_seq.pio_port = piobus.port 100 101 l1_cntrl = L1Cache_Controller(version = i, 102 sequencer = cpu_seq, 103 L1IcacheMemory = l1i_cache, 104 L1DcacheMemory = l1d_cache, 105 l2_select_num_bits = \ |
106 math.log(options.num_l2caches, 107 2), |
108 N_tokens = n_tokens, |
109 retry_threshold = \ 110 options.l1_retries, |
111 fixed_timeout_latency = \ 112 options.timeout_latency, 113 dynamic_timeout_enabled = \ 114 not options.disable_dyn_timeouts) 115 |
116 exec("system.l1_cntrl%d = l1_cntrl" % i) |
117 # 118 # Add controllers and sequencers to the appropriate lists 119 # 120 cpu_sequencers.append(cpu_seq) 121 l1_cntrl_nodes.append(l1_cntrl) 122 123 for i in xrange(options.num_l2caches): 124 # 125 # First create the Ruby objects associated with this cpu 126 # 127 l2_cache = L2Cache(size = options.l2_size, 128 assoc = options.l2_assoc) 129 130 l2_cntrl = L2Cache_Controller(version = i, 131 L2cacheMemory = l2_cache, 132 N_tokens = n_tokens) 133 |
134 exec("system.l2_cntrl%d = l2_cntrl" % i) |
135 l2_cntrl_nodes.append(l2_cntrl) 136 |
137 phys_mem_size = long(system.physmem.range.second) - \ 138 long(system.physmem.range.first) + 1 |
139 mem_module_size = phys_mem_size / options.num_dirs 140 141 for i in xrange(options.num_dirs): 142 # 143 # Create the Ruby objects associated with the directory controller 144 # 145 146 mem_cntrl = RubyMemoryControl(version = i) 147 148 dir_size = MemorySize('0B') 149 dir_size.value = mem_module_size 150 151 dir_cntrl = Directory_Controller(version = i, 152 directory = \ 153 RubyDirectoryMemory(version = i, |
154 size = \ 155 dir_size), |
156 memBuffer = mem_cntrl, 157 l2_select_num_bits = \ |
158 math.log(options.num_l2caches, 159 2)) |
160 |
161 exec("system.dir_cntrl%d = dir_cntrl" % i) |
162 dir_cntrl_nodes.append(dir_cntrl) 163 164 for i, dma_device in enumerate(dma_devices): 165 # 166 # Create the Ruby objects associated with the dma controller 167 # 168 dma_seq = DMASequencer(version = i, |
169 physMemPort = system.physmem.port, 170 physmem = system.physmem) |
171 172 dma_cntrl = DMA_Controller(version = i, 173 dma_sequencer = dma_seq) 174 |
175 exec("system.dma_cntrl%d = dma_cntrl" % i) |
176 dma_cntrl.dma_sequencer.port = dma_device.dma 177 dma_cntrl_nodes.append(dma_cntrl) 178 179 all_cntrls = l1_cntrl_nodes + \ 180 l2_cntrl_nodes + \ 181 dir_cntrl_nodes + \ 182 dma_cntrl_nodes 183 184 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) |