1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv |
34from Ruby import create_topology, create_directories |
35from Ruby import send_evicts 36 37# 38# Declare caches used by the protocol 39# 40class L1Cache(RubyCache): pass 41class L2Cache(RubyCache): pass 42 --- 22 unchanged lines hidden (view full) --- 65 66 # 67 # The ruby network creation expects the list of nodes in the system to be 68 # consistent with the NetDest list. Therefore the l1 controller nodes must be 69 # listed before the directory nodes and directory nodes before dma nodes, etc. 70 # 71 l1_cntrl_nodes = [] 72 l2_cntrl_nodes = [] |
73 dma_cntrl_nodes = [] 74 75 # 76 # Must create the individual controllers before the network to ensure the 77 # controller constructors are called before the network constructor 78 # 79 l2_bits = int(math.log(options.num_l2caches, 2)) 80 block_size_bits = int(math.log(options.cacheline_size, 2)) --- 97 unchanged lines hidden (view full) --- 178 l2_cntrl.L1RequestToL2Cache = MessageBuffer() 179 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 180 l2_cntrl.responseToL2Cache = MessageBuffer() 181 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 182 l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True) 183 l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master 184 185 |
186 # Run each of the ruby memory controllers at a ratio of the frequency of 187 # the ruby system 188 # clk_divider value is a fix to pass regression. 189 ruby_system.memctrl_clk_domain = DerivedClockDomain( 190 clk_domain=ruby_system.clk_domain, 191 clk_divider=3) 192 |
193 dir_cntrl_nodes = create_directories(options, system.mem_ranges, 194 ruby_system) 195 for dir_cntrl in dir_cntrl_nodes: 196 dir_cntrl.l2_select_num_bits = l2_bits |
197 # Connect the directory controllers and the network 198 dir_cntrl.requestToDir = MessageBuffer() 199 dir_cntrl.requestToDir.slave = ruby_system.network.master 200 dir_cntrl.responseToDir = MessageBuffer() 201 dir_cntrl.responseToDir.slave = ruby_system.network.master 202 dir_cntrl.persistentToDir = MessageBuffer(ordered = True) 203 dir_cntrl.persistentToDir.slave = ruby_system.network.master 204 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) --- 63 unchanged lines hidden --- |