1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 166 unchanged lines hidden (view full) --- 175 # Run each of the ruby memory controllers at a ratio of the frequency of 176 # the ruby system 177 # clk_divider value is a fix to pass regression. 178 ruby_system.memctrl_clk_domain = DerivedClockDomain( 179 clk_domain=ruby_system.clk_domain, 180 clk_divider=3) 181 182 for i in xrange(options.num_dirs): |
183 dir_size = MemorySize('0B') 184 dir_size.value = mem_module_size 185 186 dir_cntrl = Directory_Controller(version = i, |
187 directory = RubyDirectoryMemory( 188 version = i, size = dir_size), |
189 l2_select_num_bits = l2_bits, 190 transitions_per_cycle = options.ports, 191 ruby_system = ruby_system) 192 193 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 194 dir_cntrl_nodes.append(dir_cntrl) 195 196 # Connect the directory controllers and the network --- 54 unchanged lines hidden --- |