1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39 latency = 3
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 15
46
47def define_options(parser):
48 parser.add_option("--l1-retries", type="int", default=1,
49 help="Token_CMP: # of l1 retries before going persistent")
50 parser.add_option("--timeout-latency", type="int", default=300,
51 help="Token_CMP: cycles until issuing again");
52 parser.add_option("--disable-dyn-timeouts", action="store_true",
53 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
54
55def create_system(options, system, piobus, dma_devices):
56
57 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
58 panic("This script requires the MOESI_CMP_token protocol to be built.")
59
60 #
61 # number of tokens that the owner passes to requests so that shared blocks can
62 # respond to read requests
63 #
64 n_tokens = options.num_cpus + 1
65
66 cpu_sequencers = []
67
68 #
69 # The ruby network creation expects the list of nodes in the system to be
70 # consistent with the NetDest list. Therefore the l1 controller nodes must be
71 # listed before the directory nodes and directory nodes before dma nodes, etc.
72 #
73 l1_cntrl_nodes = []
74 l2_cntrl_nodes = []
75 dir_cntrl_nodes = []
76 dma_cntrl_nodes = []
77
78 #
79 # Must create the individual controllers before the network to ensure the
80 # controller constructors are called before the network constructor
81 #
82
83 for i in xrange(options.num_cpus):
84 #
85 # First create the Ruby objects associated with this cpu
86 #
87 l1i_cache = L1Cache(size = options.l1i_size,
88 assoc = options.l1i_assoc)
89 l1d_cache = L1Cache(size = options.l1d_size,
90 assoc = options.l1d_assoc)
91
92 cpu_seq = RubySequencer(version = i,
93 icache = l1i_cache,
94 dcache = l1d_cache,
95 physMemPort = system.physmem.port,
96 physmem = system.physmem)
97
98 if piobus != None:
99 cpu_seq.pio_port = piobus.port
100
101 l1_cntrl = L1Cache_Controller(version = i,
102 sequencer = cpu_seq,
103 L1IcacheMemory = l1i_cache,
104 L1DcacheMemory = l1d_cache,
105 l2_select_num_bits = \
106 math.log(options.num_l2caches,
107 2),
108 N_tokens = n_tokens,
109 retry_threshold = \
110 options.l1_retries,
111 fixed_timeout_latency = \
112 options.timeout_latency,
113 dynamic_timeout_enabled = \
114 not options.disable_dyn_timeouts)
115
116 exec("system.l1_cntrl%d = l1_cntrl" % i)
117 #
118 # Add controllers and sequencers to the appropriate lists
119 #
120 cpu_sequencers.append(cpu_seq)
121 l1_cntrl_nodes.append(l1_cntrl)
122
123 for i in xrange(options.num_l2caches):
124 #
125 # First create the Ruby objects associated with this cpu
126 #
127 l2_cache = L2Cache(size = options.l2_size,
128 assoc = options.l2_assoc)
129
130 l2_cntrl = L2Cache_Controller(version = i,
131 L2cacheMemory = l2_cache,
132 N_tokens = n_tokens)
133
134 exec("system.l2_cntrl%d = l2_cntrl" % i)
135 l2_cntrl_nodes.append(l2_cntrl)
136
137 phys_mem_size = long(system.physmem.range.second) - \
138 long(system.physmem.range.first) + 1
139 mem_module_size = phys_mem_size / options.num_dirs
140
141 for i in xrange(options.num_dirs):
142 #
143 # Create the Ruby objects associated with the directory controller
144 #
145
146 mem_cntrl = RubyMemoryControl(version = i)
147
148 dir_size = MemorySize('0B')
149 dir_size.value = mem_module_size
150
151 dir_cntrl = Directory_Controller(version = i,
152 directory = \
153 RubyDirectoryMemory(version = i,
154 size = \
155 dir_size),
156 memBuffer = mem_cntrl,
157 l2_select_num_bits = \
158 math.log(options.num_l2caches,
159 2))
160
161 exec("system.dir_cntrl%d = dir_cntrl" % i)
162 dir_cntrl_nodes.append(dir_cntrl)
163
164 for i, dma_device in enumerate(dma_devices):
165 #
166 # Create the Ruby objects associated with the dma controller
167 #
168 dma_seq = DMASequencer(version = i,
169 physMemPort = system.physmem.port,
170 physmem = system.physmem)
171
172 dma_cntrl = DMA_Controller(version = i,
173 dma_sequencer = dma_seq)
174
175 exec("system.dma_cntrl%d = dma_cntrl" % i)
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34
35#
36# Note: the L1 Cache latency is only used by the sequencer on fast path hits
37#
38class L1Cache(RubyCache):
39 latency = 3
40
41#
42# Note: the L2 Cache latency is not currently used
43#
44class L2Cache(RubyCache):
45 latency = 15
46
47def define_options(parser):
48 parser.add_option("--l1-retries", type="int", default=1,
49 help="Token_CMP: # of l1 retries before going persistent")
50 parser.add_option("--timeout-latency", type="int", default=300,
51 help="Token_CMP: cycles until issuing again");
52 parser.add_option("--disable-dyn-timeouts", action="store_true",
53 help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
54
55def create_system(options, system, piobus, dma_devices):
56
57 if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
58 panic("This script requires the MOESI_CMP_token protocol to be built.")
59
60 #
61 # number of tokens that the owner passes to requests so that shared blocks can
62 # respond to read requests
63 #
64 n_tokens = options.num_cpus + 1
65
66 cpu_sequencers = []
67
68 #
69 # The ruby network creation expects the list of nodes in the system to be
70 # consistent with the NetDest list. Therefore the l1 controller nodes must be
71 # listed before the directory nodes and directory nodes before dma nodes, etc.
72 #
73 l1_cntrl_nodes = []
74 l2_cntrl_nodes = []
75 dir_cntrl_nodes = []
76 dma_cntrl_nodes = []
77
78 #
79 # Must create the individual controllers before the network to ensure the
80 # controller constructors are called before the network constructor
81 #
82
83 for i in xrange(options.num_cpus):
84 #
85 # First create the Ruby objects associated with this cpu
86 #
87 l1i_cache = L1Cache(size = options.l1i_size,
88 assoc = options.l1i_assoc)
89 l1d_cache = L1Cache(size = options.l1d_size,
90 assoc = options.l1d_assoc)
91
92 cpu_seq = RubySequencer(version = i,
93 icache = l1i_cache,
94 dcache = l1d_cache,
95 physMemPort = system.physmem.port,
96 physmem = system.physmem)
97
98 if piobus != None:
99 cpu_seq.pio_port = piobus.port
100
101 l1_cntrl = L1Cache_Controller(version = i,
102 sequencer = cpu_seq,
103 L1IcacheMemory = l1i_cache,
104 L1DcacheMemory = l1d_cache,
105 l2_select_num_bits = \
106 math.log(options.num_l2caches,
107 2),
108 N_tokens = n_tokens,
109 retry_threshold = \
110 options.l1_retries,
111 fixed_timeout_latency = \
112 options.timeout_latency,
113 dynamic_timeout_enabled = \
114 not options.disable_dyn_timeouts)
115
116 exec("system.l1_cntrl%d = l1_cntrl" % i)
117 #
118 # Add controllers and sequencers to the appropriate lists
119 #
120 cpu_sequencers.append(cpu_seq)
121 l1_cntrl_nodes.append(l1_cntrl)
122
123 for i in xrange(options.num_l2caches):
124 #
125 # First create the Ruby objects associated with this cpu
126 #
127 l2_cache = L2Cache(size = options.l2_size,
128 assoc = options.l2_assoc)
129
130 l2_cntrl = L2Cache_Controller(version = i,
131 L2cacheMemory = l2_cache,
132 N_tokens = n_tokens)
133
134 exec("system.l2_cntrl%d = l2_cntrl" % i)
135 l2_cntrl_nodes.append(l2_cntrl)
136
137 phys_mem_size = long(system.physmem.range.second) - \
138 long(system.physmem.range.first) + 1
139 mem_module_size = phys_mem_size / options.num_dirs
140
141 for i in xrange(options.num_dirs):
142 #
143 # Create the Ruby objects associated with the directory controller
144 #
145
146 mem_cntrl = RubyMemoryControl(version = i)
147
148 dir_size = MemorySize('0B')
149 dir_size.value = mem_module_size
150
151 dir_cntrl = Directory_Controller(version = i,
152 directory = \
153 RubyDirectoryMemory(version = i,
154 size = \
155 dir_size),
156 memBuffer = mem_cntrl,
157 l2_select_num_bits = \
158 math.log(options.num_l2caches,
159 2))
160
161 exec("system.dir_cntrl%d = dir_cntrl" % i)
162 dir_cntrl_nodes.append(dir_cntrl)
163
164 for i, dma_device in enumerate(dma_devices):
165 #
166 # Create the Ruby objects associated with the dma controller
167 #
168 dma_seq = DMASequencer(version = i,
169 physMemPort = system.physmem.port,
170 physmem = system.physmem)
171
172 dma_cntrl = DMA_Controller(version = i,
173 dma_sequencer = dma_seq)
174
175 exec("system.dma_cntrl%d = dma_cntrl" % i)
|