MOESI_CMP_token.py (9826:014ff1fbff6d) | MOESI_CMP_token.py (9841:69c158420c51) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 100 unchanged lines hidden (view full) --- 109 fixed_timeout_latency = \ 110 options.timeout_latency, 111 dynamic_timeout_enabled = \ 112 not options.disable_dyn_timeouts, 113 no_mig_atomic = not \ 114 options.allow_atomic_migration, 115 send_evictions = ( 116 options.cpu_type == "detailed"), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 100 unchanged lines hidden (view full) --- 109 fixed_timeout_latency = \ 110 options.timeout_latency, 111 dynamic_timeout_enabled = \ 112 not options.disable_dyn_timeouts, 113 no_mig_atomic = not \ 114 options.allow_atomic_migration, 115 send_evictions = ( 116 options.cpu_type == "detailed"), |
117 transitions_per_cycle = options.ports, |
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117 ruby_system = ruby_system) 118 119 cpu_seq = RubySequencer(version = i, 120 icache = l1i_cache, 121 dcache = l1d_cache, 122 ruby_system = ruby_system) 123 124 l1_cntrl.sequencer = cpu_seq --- 19 unchanged lines hidden (view full) --- 144 l2_cache = L2Cache(size = options.l2_size, 145 assoc = options.l2_assoc, 146 start_index_bit = l2_index_start) 147 148 l2_cntrl = L2Cache_Controller(version = i, 149 cntrl_id = cntrl_count, 150 L2cache = l2_cache, 151 N_tokens = n_tokens, | 118 ruby_system = ruby_system) 119 120 cpu_seq = RubySequencer(version = i, 121 icache = l1i_cache, 122 dcache = l1d_cache, 123 ruby_system = ruby_system) 124 125 l1_cntrl.sequencer = cpu_seq --- 19 unchanged lines hidden (view full) --- 145 l2_cache = L2Cache(size = options.l2_size, 146 assoc = options.l2_assoc, 147 start_index_bit = l2_index_start) 148 149 l2_cntrl = L2Cache_Controller(version = i, 150 cntrl_id = cntrl_count, 151 L2cache = l2_cache, 152 N_tokens = n_tokens, |
153 transitions_per_cycle = options.ports, |
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152 ruby_system = ruby_system) 153 154 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 155 l2_cntrl_nodes.append(l2_cntrl) 156 157 cntrl_count += 1 158 159 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) --- 23 unchanged lines hidden (view full) --- 183 dir_cntrl = Directory_Controller(version = i, 184 cntrl_id = cntrl_count, 185 directory = \ 186 RubyDirectoryMemory(version = i, 187 use_map = options.use_map, 188 size = dir_size), 189 memBuffer = mem_cntrl, 190 l2_select_num_bits = l2_bits, | 154 ruby_system = ruby_system) 155 156 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 157 l2_cntrl_nodes.append(l2_cntrl) 158 159 cntrl_count += 1 160 161 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) --- 23 unchanged lines hidden (view full) --- 185 dir_cntrl = Directory_Controller(version = i, 186 cntrl_id = cntrl_count, 187 directory = \ 188 RubyDirectoryMemory(version = i, 189 use_map = options.use_map, 190 size = dir_size), 191 memBuffer = mem_cntrl, 192 l2_select_num_bits = l2_bits, |
193 transitions_per_cycle = options.ports, |
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191 ruby_system = ruby_system) 192 193 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 194 dir_cntrl_nodes.append(dir_cntrl) 195 196 cntrl_count += 1 197 198 for i, dma_port in enumerate(dma_ports): 199 # 200 # Create the Ruby objects associated with the dma controller 201 # 202 dma_seq = DMASequencer(version = i, 203 ruby_system = ruby_system) 204 205 dma_cntrl = DMA_Controller(version = i, 206 cntrl_id = cntrl_count, 207 dma_sequencer = dma_seq, | 194 ruby_system = ruby_system) 195 196 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 197 dir_cntrl_nodes.append(dir_cntrl) 198 199 cntrl_count += 1 200 201 for i, dma_port in enumerate(dma_ports): 202 # 203 # Create the Ruby objects associated with the dma controller 204 # 205 dma_seq = DMASequencer(version = i, 206 ruby_system = ruby_system) 207 208 dma_cntrl = DMA_Controller(version = i, 209 cntrl_id = cntrl_count, 210 dma_sequencer = dma_seq, |
211 transitions_per_cycle = options.ports, |
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208 ruby_system = ruby_system) 209 210 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 211 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 212 dma_cntrl_nodes.append(dma_cntrl) 213 cntrl_count += 1 214 215 all_cntrls = l1_cntrl_nodes + \ 216 l2_cntrl_nodes + \ 217 dir_cntrl_nodes + \ 218 dma_cntrl_nodes 219 220 topology = create_topology(all_cntrls, options) 221 222 return (cpu_sequencers, dir_cntrl_nodes, topology) | 212 ruby_system = ruby_system) 213 214 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 215 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 216 dma_cntrl_nodes.append(dma_cntrl) 217 cntrl_count += 1 218 219 all_cntrls = l1_cntrl_nodes + \ 220 l2_cntrl_nodes + \ 221 dir_cntrl_nodes + \ 222 dma_cntrl_nodes 223 224 topology = create_topology(all_cntrls, options) 225 226 return (cpu_sequencers, dir_cntrl_nodes, topology) |