MOESI_CMP_token.py (10116:d61a59beb670) | MOESI_CMP_token.py (10300:ed3816dae6d5) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 98 unchanged lines hidden (view full) --- 107 options.timeout_latency, 108 dynamic_timeout_enabled = \ 109 not options.disable_dyn_timeouts, 110 no_mig_atomic = not \ 111 options.allow_atomic_migration, 112 send_evictions = ( 113 options.cpu_type == "detailed"), 114 transitions_per_cycle = options.ports, | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 98 unchanged lines hidden (view full) --- 107 options.timeout_latency, 108 dynamic_timeout_enabled = \ 109 not options.disable_dyn_timeouts, 110 no_mig_atomic = not \ 111 options.allow_atomic_migration, 112 send_evictions = ( 113 options.cpu_type == "detailed"), 114 transitions_per_cycle = options.ports, |
115 clk_domain=system.cpu[i].clk_domain, |
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115 ruby_system = ruby_system) 116 117 cpu_seq = RubySequencer(version = i, 118 icache = l1i_cache, 119 dcache = l1d_cache, | 116 ruby_system = ruby_system) 117 118 cpu_seq = RubySequencer(version = i, 119 icache = l1i_cache, 120 dcache = l1d_cache, |
121 clk_domain=system.cpu[i].clk_domain, |
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120 ruby_system = ruby_system) 121 122 l1_cntrl.sequencer = cpu_seq 123 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 124 125 # 126 # Add controllers and sequencers to the appropriate lists 127 # --- 83 unchanged lines hidden --- | 122 ruby_system = ruby_system) 123 124 l1_cntrl.sequencer = cpu_seq 125 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 126 127 # 128 # Add controllers and sequencers to the appropriate lists 129 # --- 83 unchanged lines hidden --- |