1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 141 unchanged lines hidden (view full) ---

150 L2cacheMemory = l2_cache,
151 N_tokens = n_tokens,
152 ruby_system = ruby_system)
153
154 exec("system.l2_cntrl%d = l2_cntrl" % i)
155 l2_cntrl_nodes.append(l2_cntrl)
156
157 cntrl_count += 1
158
159 phys_mem_size = 0
160 for mem in system.memories.unproxy(system):
161 phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
162 mem_module_size = phys_mem_size / options.num_dirs
163
164 for i in xrange(options.num_dirs):
165 #
166 # Create the Ruby objects associated with the directory controller
167 #
168
169 mem_cntrl = RubyMemoryControl(version = i,

--- 44 unchanged lines hidden ---